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Searched refs:pin_cfg (Results 1 – 15 of 15) sorted by relevance

/Zephyr-latest/drivers/pinctrl/
Dpinctrl_xmc4xxx.c20 XMC_GPIO_CONFIG_t pin_cfg = {0}; in pinctrl_configure_pin() local
31 pin_cfg.mode = XMC_GPIO_MODE_INPUT_PULL_DOWN; in pinctrl_configure_pin()
35 pin_cfg.mode = XMC_GPIO_MODE_INPUT_PULL_UP; in pinctrl_configure_pin()
39 pin_cfg.mode |= 0x4; in pinctrl_configure_pin()
43 pin_cfg.mode = XMC_GPIO_MODE_OUTPUT_OPEN_DRAIN; in pinctrl_configure_pin()
47 pin_cfg.mode = XMC_GPIO_MODE_OUTPUT_PUSH_PULL; in pinctrl_configure_pin()
51 pin_cfg.mode |= alt_fun << PORT0_IOCR0_PC0_Pos; in pinctrl_configure_pin()
55 pin_cfg.output_level = XMC_GPIO_OUTPUT_LEVEL_HIGH; in pinctrl_configure_pin()
60 pin_cfg.output_level = XMC_GPIO_OUTPUT_LEVEL_LOW; in pinctrl_configure_pin()
64 pin_cfg.output_strength = XMC4XXX_PINMUX_GET_DRIVE(pinmux); in pinctrl_configure_pin()
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Dpinctrl_esp32.c178 static int esp32_pin_configure(const uint32_t pin_mux, const uint32_t pin_cfg) in esp32_pin_configure() argument
196 switch (ESP32_PIN_BIAS(pin_cfg)) { in esp32_pin_configure()
207 switch (ESP32_PIN_DRV(pin_cfg)) { in esp32_pin_configure()
230 switch (ESP32_PIN_MODE_OUT(pin_cfg)) { in esp32_pin_configure()
241 switch (ESP32_PIN_EN_DIR(pin_cfg)) { in esp32_pin_configure()
296 uint32_t pin_mux, pin_cfg; in pinctrl_configure_pins() local
303 pin_cfg = pins[i].pincfg; in pinctrl_configure_pins()
305 ret = esp32_pin_configure(pin_mux, pin_cfg); in pinctrl_configure_pins()
/Zephyr-latest/tests/drivers/input/gpio_keys/src/
Dmain.c28 const struct gpio_keys_pin_config *pin_cfg; member
56 const struct gpio_keys_pin_config *pin_cfg = &config->pin_cfg[BUTTON_0_IDX]; in ZTEST() local
57 const struct gpio_dt_spec *spec = &pin_cfg->spec; in ZTEST()
71 zassert_equal(last_code, pin_cfg->zephyr_code); in ZTEST()
83 zassert_equal(last_code, pin_cfg->zephyr_code); in ZTEST()
/Zephyr-latest/soc/nxp/rw/
Dpower.c32 pinctrl_soc_pin_t pin_cfg; variable
65 pin_cfg = IOMUX_GPIO_IDX(24) | IOMUX_TYPE(IOMUX_GPIO); in pm_state_set()
66 pinctrl_configure_pins(&pin_cfg, 1, 0); in pm_state_set()
74 pin_cfg = IOMUX_GPIO_IDX(25) | IOMUX_TYPE(IOMUX_GPIO); in pm_state_set()
75 pinctrl_configure_pins(&pin_cfg, 1, 0); in pm_state_set()
124 pin_cfg = IOMUX_GPIO_IDX(24) | IOMUX_TYPE(IOMUX_GPIO); in nxp_rw6xx_power_init()
125 pinctrl_configure_pins(&pin_cfg, 1, 0); in nxp_rw6xx_power_init()
136 pin_cfg = IOMUX_GPIO_IDX(25) | IOMUX_TYPE(IOMUX_GPIO); in nxp_rw6xx_power_init()
137 pinctrl_configure_pins(&pin_cfg, 1, 0); in nxp_rw6xx_power_init()
/Zephyr-latest/drivers/input/
Dinput_gpio_keys.c43 const struct gpio_keys_pin_config *pin_cfg; member
62 const struct gpio_keys_pin_config *pin_cfg = &cfg->pin_cfg[key_index]; in gpio_keys_poll_pin() local
67 ret = gpio_pin_get_dt(&pin_cfg->spec); in gpio_keys_poll_pin()
81 pin_cfg->zephyr_code); in gpio_keys_poll_pin()
82 input_report_key(dev, pin_cfg->zephyr_code, new_pressed, true, K_FOREVER); in gpio_keys_poll_pin()
175 const struct gpio_dt_spec *gpio = &cfg->pin_cfg[i].spec; in gpio_keys_init()
195 ret = gpio_keys_interrupt_configure(&cfg->pin_cfg[i].spec, in gpio_keys_init()
197 cfg->pin_cfg[i].zephyr_code); in gpio_keys_init()
232 const struct gpio_dt_spec *gpio = &cfg->pin_cfg[i].spec; in gpio_keys_pm_action()
256 const struct gpio_dt_spec *gpio = &cfg->pin_cfg[i].spec; in gpio_keys_pm_action()
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/Zephyr-latest/drivers/serial/
Duart_wch_usart.c22 const struct pinctrl_dev_config *pin_cfg; member
64 err = pinctrl_apply_state(config->pin_cfg, PINCTRL_STATE_DEFAULT); in usart_wch_init()
134 .pin_cfg = PINCTRL_DT_INST_DEV_CONFIG_GET(idx), \
/Zephyr-latest/drivers/gpio/
Dgpio_mcux_rgpio.c50 struct pinctrl_soc_pin pin_cfg; in mcux_rgpio_configure() local
132 memcpy(&pin_cfg.pinmux, &config->pin_muxes[cfg_idx], sizeof(pin_cfg)); in mcux_rgpio_configure()
134 pin_cfg.pin_ctrl_flags = reg; in mcux_rgpio_configure()
135 pinctrl_configure_pins(&pin_cfg, 1, PINCTRL_REG_NONE); in mcux_rgpio_configure()
Dgpio_imx.c47 struct pinctrl_soc_pin pin_cfg; in imx_gpio_configure() local
86 memcpy(&pin_cfg.pinmux, &config->pin_muxes[pin], sizeof(pin_cfg.pinmux)); in imx_gpio_configure()
91 pin_cfg.pin_ctrl_flags = reg; in imx_gpio_configure()
92 pinctrl_configure_pins(&pin_cfg, 1, PINCTRL_REG_NONE); in imx_gpio_configure()
Dgpio_mcux_igpio.c57 struct pinctrl_soc_pin pin_cfg; in mcux_igpio_configure() local
197 memcpy(&pin_cfg.pinmux, &config->pin_muxes[cfg_idx], sizeof(pin_cfg.pinmux)); in mcux_igpio_configure()
199 pin_cfg.pin_ctrl_flags = reg; in mcux_igpio_configure()
200 pinctrl_configure_pins(&pin_cfg, 1, PINCTRL_REG_NONE); in mcux_igpio_configure()
Dgpio_mcux_lpc.c113 pinctrl_soc_pin_t pin_cfg; in gpio_mcux_lpc_configure() local
116 pin_cfg = IOMUX_GPIO_IDX(pin + 32) | IOMUX_TYPE(IOMUX_GPIO); in gpio_mcux_lpc_configure()
118 pin_cfg = IOMUX_GPIO_IDX(pin) | IOMUX_TYPE(IOMUX_GPIO); in gpio_mcux_lpc_configure()
122 pin_cfg |= IOMUX_PAD_PULL(0x1); in gpio_mcux_lpc_configure()
124 pin_cfg |= IOMUX_PAD_PULL(0x2); in gpio_mcux_lpc_configure()
126 pinctrl_configure_pins(&pin_cfg, 1, 0); in gpio_mcux_lpc_configure()
Dgpio_stm32.c101 static int gpio_stm32_pincfg_to_flags(struct gpio_stm32_pin pin_cfg, in gpio_stm32_pincfg_to_flags() argument
106 if (pin_cfg.mode == LL_GPIO_MODE_OUTPUT) { in gpio_stm32_pincfg_to_flags()
108 if (pin_cfg.type == LL_GPIO_OUTPUT_OPENDRAIN) { in gpio_stm32_pincfg_to_flags()
111 } else if (pin_cfg.mode == LL_GPIO_MODE_INPUT) { in gpio_stm32_pincfg_to_flags()
114 } else if (pin_cfg.mode == LL_GPIO_MODE_FLOATING) { in gpio_stm32_pincfg_to_flags()
121 if (pin_cfg.pupd == LL_GPIO_PULL_UP) { in gpio_stm32_pincfg_to_flags()
123 } else if (pin_cfg.pupd == LL_GPIO_PULL_DOWN) { in gpio_stm32_pincfg_to_flags()
127 if (pin_cfg.out_state != 0) { in gpio_stm32_pincfg_to_flags()
/Zephyr-latest/drivers/adc/
Dadc_nxp_s32_adc_sar.c32 const struct pinctrl_dev_config *pin_cfg; member
56 if (config->pin_cfg) { in adc_nxp_s32_init()
57 if (pinctrl_apply_state(config->pin_cfg, PINCTRL_STATE_DEFAULT)) { in adc_nxp_s32_init()
446 .pin_cfg = COND_CODE_1(DT_INST_NUM_PINCTRL_STATES(n), \
Dadc_ambiq.c34 const struct pinctrl_dev_config *pin_cfg; member
316 ret = pinctrl_apply_state(cfg->pin_cfg, PINCTRL_STATE_DEFAULT); in adc_ambiq_init()
431 .pin_cfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n), \
/Zephyr-latest/drivers/spi/
Dspi_rpi_pico_pio.c33 const struct pinctrl_dev_config *pin_cfg; member
710 rc = pinctrl_apply_state(dev_cfg->pin_cfg, PINCTRL_STATE_DEFAULT); in spi_pico_pio_init()
750 .pin_cfg = PINCTRL_DT_INST_DEV_CONFIG_GET(inst), \
/Zephyr-latest/drivers/can/
Dcan_nxp_s32_canxl.c83 const struct pinctrl_dev_config *pin_cfg; member
984 err = pinctrl_apply_state(config->pin_cfg, PINCTRL_STATE_DEFAULT); in can_nxp_s32_init()
1235 .pin_cfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n), \