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/Zephyr-latest/drivers/dma/
Ddma_stm32_v1.c20 uint32_t dma_stm32_id_to_stream(uint32_t id) in dma_stm32_id_to_stream() argument
33 __ASSERT_NO_MSG(id < ARRAY_SIZE(stream_nr)); in dma_stm32_id_to_stream()
35 return stream_nr[id]; in dma_stm32_id_to_stream()
58 void dma_stm32_clear_ht(DMA_TypeDef *DMAx, uint32_t id) in dma_stm32_clear_ht() argument
71 __ASSERT_NO_MSG(id < ARRAY_SIZE(func)); in dma_stm32_clear_ht()
73 func[id](DMAx); in dma_stm32_clear_ht()
76 void dma_stm32_clear_tc(DMA_TypeDef *DMAx, uint32_t id) in dma_stm32_clear_tc() argument
89 __ASSERT_NO_MSG(id < ARRAY_SIZE(func)); in dma_stm32_clear_tc()
91 func[id](DMAx); in dma_stm32_clear_tc()
94 bool dma_stm32_is_ht_active(DMA_TypeDef *DMAx, uint32_t id) in dma_stm32_is_ht_active() argument
[all …]
Ddma_stm32_v2.c18 uint32_t dma_stm32_id_to_stream(uint32_t id) in dma_stm32_id_to_stream() argument
39 __ASSERT_NO_MSG(id < ARRAY_SIZE(stream_nr)); in dma_stm32_id_to_stream()
41 return stream_nr[id]; in dma_stm32_id_to_stream()
44 void dma_stm32_clear_ht(DMA_TypeDef *DMAx, uint32_t id) in dma_stm32_clear_ht() argument
65 __ASSERT_NO_MSG(id < ARRAY_SIZE(func)); in dma_stm32_clear_ht()
67 func[id](DMAx); in dma_stm32_clear_ht()
70 void dma_stm32_clear_tc(DMA_TypeDef *DMAx, uint32_t id) in dma_stm32_clear_tc() argument
91 __ASSERT_NO_MSG(id < ARRAY_SIZE(func)); in dma_stm32_clear_tc()
93 func[id](DMAx); in dma_stm32_clear_tc()
96 bool dma_stm32_is_ht_active(DMA_TypeDef *DMAx, uint32_t id) in dma_stm32_is_ht_active() argument
[all …]
Ddma_stm32u5.c46 static void dma_stm32_dump_stream_irq(const struct device *dev, uint32_t id) in dma_stm32_dump_stream_irq() argument
51 stm32_dma_dump_stream_irq(dma, id); in dma_stm32_dump_stream_irq()
54 static void dma_stm32_clear_stream_irq(const struct device *dev, uint32_t id) in dma_stm32_clear_stream_irq() argument
59 dma_stm32_clear_tc(dma, id); in dma_stm32_clear_stream_irq()
60 dma_stm32_clear_ht(dma, id); in dma_stm32_clear_stream_irq()
61 stm32_dma_clear_stream_irq(dma, id); in dma_stm32_clear_stream_irq()
65 uint32_t dma_stm32_id_to_stream(uint32_t id) in dma_stm32_id_to_stream() argument
86 __ASSERT_NO_MSG(id < ARRAY_SIZE(stream_nr)); in dma_stm32_id_to_stream()
88 return stream_nr[id]; in dma_stm32_id_to_stream()
91 bool dma_stm32_is_tc_active(DMA_TypeDef *DMAx, uint32_t id) in dma_stm32_is_tc_active() argument
[all …]
Ddma_stm32.h49 uint32_t dma_stm32_id_to_stream(uint32_t id);
51 uint32_t dma_stm32_slot_to_channel(uint32_t id);
63 bool dma_stm32_is_tc_active(DMA_TypeDef *DMAx, uint32_t id);
64 void dma_stm32_clear_tc(DMA_TypeDef *DMAx, uint32_t id);
65 bool dma_stm32_is_ht_active(DMA_TypeDef *DMAx, uint32_t id);
66 void dma_stm32_clear_ht(DMA_TypeDef *DMAx, uint32_t id);
67 bool dma_stm32_is_te_active(DMA_TypeDef *DMAx, uint32_t id);
68 void dma_stm32_clear_te(DMA_TypeDef *DMAx, uint32_t id);
71 bool dma_stm32_is_dme_active(DMA_TypeDef *DMAx, uint32_t id);
72 void dma_stm32_clear_dme(DMA_TypeDef *DMAx, uint32_t id);
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Ddma_stm32_bdma.c38 uint32_t bdma_stm32_id_to_channel(uint32_t id) in bdma_stm32_id_to_channel() argument
51 __ASSERT_NO_MSG(id < ARRAY_SIZE(channel_nr)); in bdma_stm32_id_to_channel()
53 return channel_nr[id]; in bdma_stm32_id_to_channel()
76 void bdma_stm32_clear_ht(BDMA_TypeDef *DMAx, uint32_t id) in bdma_stm32_clear_ht() argument
89 __ASSERT_NO_MSG(id < ARRAY_SIZE(func)); in bdma_stm32_clear_ht()
91 func[id](DMAx); in bdma_stm32_clear_ht()
94 void bdma_stm32_clear_tc(BDMA_TypeDef *DMAx, uint32_t id) in bdma_stm32_clear_tc() argument
107 __ASSERT_NO_MSG(id < ARRAY_SIZE(func)); in bdma_stm32_clear_tc()
109 func[id](DMAx); in bdma_stm32_clear_tc()
112 bool bdma_stm32_is_ht_active(BDMA_TypeDef *DMAx, uint32_t id) in bdma_stm32_is_ht_active() argument
[all …]
Ddma_stm32_bdma.h50 uint32_t bdma_stm32_id_to_channel(uint32_t id);
52 uint32_t bdma_stm32_slot_to_channel(uint32_t id);
58 bool bdma_stm32_is_gi_active(BDMA_TypeDef *DMAx, uint32_t id);
59 void bdma_stm32_clear_gi(BDMA_TypeDef *DMAx, uint32_t id);
61 void bdma_stm32_clear_tc(BDMA_TypeDef *DMAx, uint32_t id);
62 void bdma_stm32_clear_ht(BDMA_TypeDef *DMAx, uint32_t id);
63 bool bdma_stm32_is_te_active(BDMA_TypeDef *DMAx, uint32_t id);
64 void bdma_stm32_clear_te(BDMA_TypeDef *DMAx, uint32_t id);
66 bool stm32_bdma_is_irq_active(BDMA_TypeDef *dma, uint32_t id);
67 bool stm32_bdma_is_ht_irq_active(BDMA_TypeDef *ma, uint32_t id);
[all …]
Ddma_stm32.c70 static void dma_stm32_dump_stream_irq(const struct device *dev, uint32_t id) in dma_stm32_dump_stream_irq() argument
75 stm32_dma_dump_stream_irq(dma, id); in dma_stm32_dump_stream_irq()
78 static void dma_stm32_clear_stream_irq(const struct device *dev, uint32_t id) in dma_stm32_clear_stream_irq() argument
83 dma_stm32_clear_tc(dma, id); in dma_stm32_clear_stream_irq()
84 dma_stm32_clear_ht(dma, id); in dma_stm32_clear_stream_irq()
85 stm32_dma_clear_stream_irq(dma, id); in dma_stm32_clear_stream_irq()
88 static void dma_stm32_irq_handler(const struct device *dev, uint32_t id) in dma_stm32_irq_handler() argument
95 __ASSERT_NO_MSG(id < config->max_streams); in dma_stm32_irq_handler()
97 stream = &config->streams[id]; in dma_stm32_irq_handler()
105 dma_stm32_clear_stream_irq(dev, id); in dma_stm32_irq_handler()
[all …]
/Zephyr-latest/soc/atmel/sam/common/
Dsoc_pmc.c19 void soc_pmc_peripheral_enable(uint32_t id) in soc_pmc_peripheral_enable() argument
21 __ASSERT(id < ID_PERIPH_COUNT, "Invalid peripheral id"); in soc_pmc_peripheral_enable()
23 if (id < 32) { in soc_pmc_peripheral_enable()
24 PMC->PMC_PCER0 = BIT(id); in soc_pmc_peripheral_enable()
26 } else if (id < 64) { in soc_pmc_peripheral_enable()
27 PMC->PMC_PCER1 = BIT(id & 0x1F); in soc_pmc_peripheral_enable()
36 void soc_pmc_peripheral_disable(uint32_t id) in soc_pmc_peripheral_disable() argument
38 __ASSERT(id < ID_PERIPH_COUNT, "Invalid peripheral id"); in soc_pmc_peripheral_disable()
40 if (id < 32) { in soc_pmc_peripheral_disable()
41 PMC->PMC_PCDR0 = BIT(id); in soc_pmc_peripheral_disable()
[all …]
/Zephyr-latest/subsys/tracing/ctf/tsdl/
Dmetadata12 uint8_t id;
27 id = 0x10;
36 id = 0x11;
45 id = 0x12;
56 id = 0x13;
65 id = 0x14;
74 id = 0x15;
83 id = 0x16;
91 id = 0x17;
100 id = 0x18;
[all …]
/Zephyr-latest/drivers/reset/
Dreset_nxp_rstctl.c15 #define NXP_RSTCTL_OFFSET(id) ((id >> 16) * sizeof(uint32_t)) argument
16 #define NXP_RSTCTL_BIT(id) (BIT(id & 0xFFFF)) argument
17 #define NXP_RSTCTL_CTL(id) (NXP_RSTCTL_OFFSET(id) + 0x10) argument
18 #define NXP_RSTCTL_SET(id) (NXP_RSTCTL_OFFSET(id) + 0x40) argument
19 #define NXP_RSTCTL_CLR(id) (NXP_RSTCTL_OFFSET(id) + 0x70) argument
21 static int reset_nxp_rstctl_status(const struct device *dev, uint32_t id, uint8_t *status) in reset_nxp_rstctl_status() argument
24 volatile const uint32_t *ctl_reg = base+(NXP_RSTCTL_CTL(id)/sizeof(uint32_t)); in reset_nxp_rstctl_status()
27 *status = (uint8_t)FIELD_GET(NXP_RSTCTL_BIT(id), val); in reset_nxp_rstctl_status()
32 static int reset_nxp_rstctl_line_assert(const struct device *dev, uint32_t id) in reset_nxp_rstctl_line_assert() argument
35 volatile uint32_t *set_reg = (uint32_t *)base+(NXP_RSTCTL_SET(id)/sizeof(uint32_t)); in reset_nxp_rstctl_line_assert()
[all …]
Dreset_stm32.c14 #define STM32_RESET_CLR_OFFSET(id) (((id) >> 17U) & 0xFFFU) argument
15 #define STM32_RESET_SET_OFFSET(id) (((id) >> 5U) & 0xFFFU) argument
16 #define STM32_RESET_REG_BIT(id) ((id)&0x1FU) argument
22 static int reset_stm32_status(const struct device *dev, uint32_t id, in reset_stm32_status() argument
27 *status = !!sys_test_bit(config->base + STM32_RESET_SET_OFFSET(id), in reset_stm32_status()
28 STM32_RESET_REG_BIT(id)); in reset_stm32_status()
33 static int reset_stm32_line_assert(const struct device *dev, uint32_t id) in reset_stm32_line_assert() argument
37 sys_set_bit(config->base + STM32_RESET_SET_OFFSET(id), in reset_stm32_line_assert()
38 STM32_RESET_REG_BIT(id)); in reset_stm32_line_assert()
43 static int reset_stm32_line_deassert(const struct device *dev, uint32_t id) in reset_stm32_line_deassert() argument
[all …]
Dreset_lpc_syscon.c15 #define LPC_RESET_OFFSET(id) (id >> 16) argument
16 #define LPC_RESET_BIT(id) (BIT(id & 0xFFFF)) argument
18 static int reset_nxp_syscon_status(const struct device *dev, uint32_t id, uint8_t *status) in reset_nxp_syscon_status() argument
20 const volatile uint32_t *ctrl_reg = ((uint32_t *)dev->config)+(LPC_RESET_OFFSET(id)); in reset_nxp_syscon_status()
21 *status = (uint8_t)FIELD_GET((uint32_t)LPC_RESET_BIT(id), *ctrl_reg); in reset_nxp_syscon_status()
26 static int reset_nxp_syscon_line_assert(const struct device *dev, uint32_t id) in reset_nxp_syscon_line_assert() argument
28 SYSCON->PRESETCTRLSET[LPC_RESET_OFFSET(id)] = FIELD_PREP(LPC_RESET_BIT(id), 0b1); in reset_nxp_syscon_line_assert()
33 static int reset_nxp_syscon_line_deassert(const struct device *dev, uint32_t id) in reset_nxp_syscon_line_deassert() argument
35 SYSCON->PRESETCTRLCLR[LPC_RESET_OFFSET(id)] = FIELD_PREP(LPC_RESET_BIT(id), 0b1); in reset_nxp_syscon_line_deassert()
40 static int reset_nxp_syscon_line_toggle(const struct device *dev, uint32_t id) in reset_nxp_syscon_line_toggle() argument
[all …]
Dreset_gd32.c15 #define GD32_RESET_ID_OFFSET(id) (((id) >> 6U) & 0xFFU) argument
17 #define GD32_RESET_ID_BIT(id) ((id) & 0x1FU) argument
23 static int reset_gd32_status(const struct device *dev, uint32_t id, in reset_gd32_status() argument
28 *status = !!sys_test_bit(config->base + GD32_RESET_ID_OFFSET(id), in reset_gd32_status()
29 GD32_RESET_ID_BIT(id)); in reset_gd32_status()
34 static int reset_gd32_line_assert(const struct device *dev, uint32_t id) in reset_gd32_line_assert() argument
38 sys_set_bit(config->base + GD32_RESET_ID_OFFSET(id), in reset_gd32_line_assert()
39 GD32_RESET_ID_BIT(id)); in reset_gd32_line_assert()
44 static int reset_gd32_line_deassert(const struct device *dev, uint32_t id) in reset_gd32_line_deassert() argument
48 sys_clear_bit(config->base + GD32_RESET_ID_OFFSET(id), in reset_gd32_line_deassert()
[all …]
Dreset_numaker.c16 #define NUMAKER_RESET_IP_OFFSET(id) (NUMAKER_RESET_IPRST0_OFFSET + (((id) >> 24UL) & 0xffUL)) argument
18 #define NUMAKER_RESET_IP_BIT(id) (id & 0x00ffffffUL) argument
24 static int reset_numaker_status(const struct device *dev, uint32_t id, uint8_t *status) in reset_numaker_status() argument
28 *status = !!sys_test_bit(config->base + NUMAKER_RESET_IP_OFFSET(id), in reset_numaker_status()
29 NUMAKER_RESET_IP_BIT(id)); in reset_numaker_status()
34 static int reset_numaker_line_assert(const struct device *dev, uint32_t id) in reset_numaker_line_assert() argument
39 sys_set_bit(config->base + NUMAKER_RESET_IP_OFFSET(id), NUMAKER_RESET_IP_BIT(id)); in reset_numaker_line_assert()
44 static int reset_numaker_line_deassert(const struct device *dev, uint32_t id) in reset_numaker_line_deassert() argument
49 sys_clear_bit(config->base + NUMAKER_RESET_IP_OFFSET(id), NUMAKER_RESET_IP_BIT(id)); in reset_numaker_line_deassert()
54 static int reset_numaker_line_toggle(const struct device *dev, uint32_t id) in reset_numaker_line_toggle() argument
[all …]
Dreset_ast10x0.c33 static int aspeed_reset_line_assert(const struct device *dev, uint32_t id) in aspeed_reset_line_assert() argument
39 if (id >= ASPEED_RESET_GRP_1_OFFSET) { in aspeed_reset_line_assert()
40 id -= ASPEED_RESET_GRP_1_OFFSET; in aspeed_reset_line_assert()
44 return syscon_write_reg(syscon, addr, BIT(id)); in aspeed_reset_line_assert()
47 static int aspeed_reset_line_deassert(const struct device *dev, uint32_t id) in aspeed_reset_line_deassert() argument
53 if (id >= ASPEED_RESET_GRP_1_OFFSET) { in aspeed_reset_line_deassert()
54 id -= ASPEED_RESET_GRP_1_OFFSET; in aspeed_reset_line_deassert()
58 return syscon_write_reg(syscon, addr, BIT(id)); in aspeed_reset_line_deassert()
61 static int aspeed_reset_status(const struct device *dev, uint32_t id, uint8_t *status) in aspeed_reset_status() argument
69 if (id >= ASPEED_RESET_GRP_1_OFFSET) { in aspeed_reset_status()
[all …]
/Zephyr-latest/subsys/pm/
Dpm.c65 callback(z_cpus_pm_state[_current_cpu->id].state); in pm_state_notify()
96 uint8_t id = _current_cpu->id; in pm_system_resume() local
110 if (atomic_test_and_clear_bit(z_post_ops_required, id)) { in pm_system_resume()
113 if ((z_cpus_pm_state[id].state != PM_STATE_RUNTIME_IDLE) && in pm_system_resume()
114 !z_cpus_pm_state[id].pm_device_disabled) { in pm_system_resume()
119 pm_state_exit_post_ops(z_cpus_pm_state[id].state, z_cpus_pm_state[id].substate_id); in pm_system_resume()
124 z_cpus_pm_state[id] = (struct pm_state_info){PM_STATE_ACTIVE, 0, false, in pm_system_resume()
145 uint8_t id = _current_cpu->id; in pm_system_suspend() local
159 if (z_cpus_pm_forced_state[id].state != PM_STATE_ACTIVE) { in pm_system_suspend()
160 z_cpus_pm_state[id] = z_cpus_pm_forced_state[id]; in pm_system_suspend()
[all …]
/Zephyr-latest/include/zephyr/drivers/dma/
Ddma_stm32.h35 #define STM32_DMA_SLOT(id, dir, slot) 0 argument
36 #define STM32_DMA_SLOT_BY_IDX(id, idx, slot) 0 argument
38 #define STM32_DMA_SLOT(id, dir, slot) DT_INST_DMAS_CELL_BY_NAME(id, dir, slot) argument
39 #define STM32_DMA_SLOT_BY_IDX(id, idx, slot) DT_INST_DMAS_CELL_BY_IDX(id, idx, slot) argument
45 #define STM32_DMA_FEATURES(id, dir) 0 argument
47 #define STM32_DMA_FEATURES(id, dir) \ argument
48 DT_INST_DMAS_CELL_BY_NAME(id, dir, features)
51 #define STM32_DMA_CTLR(id, dir) \ argument
52 DT_INST_DMAS_CTLR_BY_NAME(id, dir)
53 #define STM32_DMA_CHANNEL_CONFIG(id, dir) \ argument
[all …]
/Zephyr-latest/include/zephyr/app_memory/
Dapp_memdomain.h30 #define K_APP_DMEM_SECTION(id) data_smem_##id##_data argument
40 #define K_APP_BMEM_SECTION(id) data_smem_##id##_bss argument
51 #define K_APP_DMEM(id) Z_GENERIC_SECTION(K_APP_DMEM_SECTION(id)) argument
61 #define K_APP_BMEM(id) Z_GENERIC_SECTION(K_APP_BMEM_SECTION(id)) argument
68 #define Z_APP_START(id) z_data_smem_##id##_part_start argument
69 #define Z_APP_SIZE(id) z_data_smem_##id##_part_size argument
70 #define Z_APP_BSS_START(id) z_data_smem_##id##_bss_start argument
71 #define Z_APP_BSS_SIZE(id) z_data_smem_##id##_bss_size argument
/Zephyr-latest/drivers/i2c/
Di2c_nrfx_twis.c19 #define SHIM_NRF_TWIS_NODE(id) \ argument
20 DT_NODELABEL(_CONCAT(i2c, id))
22 #define SHIM_NRF_TWIS_DEVICE_GET(id) \ argument
23 DEVICE_DT_GET(SHIM_NRF_TWIS_NODE(id))
25 #define SHIM_NRF_TWIS_IRQ_HANDLER(id) \ argument
26 _CONCAT_3(nrfx_twis_, id, _irq_handler)
28 #define SHIM_NRF_TWIS_IRQN(id) \ argument
29 DT_IRQN(SHIM_NRF_TWIS_NODE(id))
31 #define SHIM_NRF_TWIS_IRQ_PRIO(id) \ argument
32 DT_IRQ(SHIM_NRF_TWIS_NODE(id), priority)
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/Zephyr-latest/drivers/mipi_dsi/
Ddsi_renesas_ra.c211 #define IRQ_CONFIGURE_FUNC(id) \ argument
212 static void mipi_dsi_ra_configure_func_##id(void) \
214 R_ICU->IELSR[DT_INST_IRQ_BY_NAME(id, sq0, irq)] = ELC_EVENT_MIPIDSI_SEQ0; \
215 IRQ_CONNECT(DT_INST_IRQ_BY_NAME(id, sq0, irq), \
216 DT_INST_IRQ_BY_NAME(id, sq0, priority), mipi_dsi_seq0, \
217 DEVICE_DT_INST_GET(id), 0); \
218 irq_enable(DT_INST_IRQ_BY_NAME(id, sq0, irq)); \
219 R_ICU->IELSR[DT_INST_IRQ_BY_NAME(id, ferr, irq)] = ELC_EVENT_MIPIDSI_FERR; \
220 IRQ_CONNECT(DT_INST_IRQ_BY_NAME(id, ferr, irq), \
221 DT_INST_IRQ_BY_NAME(id, ferr, priority), mipi_dsi_ferr, \
[all …]
/Zephyr-latest/include/zephyr/drivers/
Dreset.h38 uint32_t id; member
74 .id = DT_RESET_ID_BY_IDX(node_id, idx) \
176 typedef int (*reset_api_status)(const struct device *dev, uint32_t id, uint8_t *status);
183 typedef int (*reset_api_line_assert)(const struct device *dev, uint32_t id);
190 typedef int (*reset_api_line_deassert)(const struct device *dev, uint32_t id);
197 typedef int (*reset_api_line_toggle)(const struct device *dev, uint32_t id);
224 __syscall int reset_status(const struct device *dev, uint32_t id, uint8_t *status);
226 static inline int z_impl_reset_status(const struct device *dev, uint32_t id, uint8_t *status) in z_impl_reset_status() argument
234 return api->status(dev, id, status); in z_impl_reset_status()
251 return reset_status(spec->dev, spec->id, status); in reset_status_dt()
[all …]
/Zephyr-latest/drivers/hwspinlock/
Dsqn_hwspinlock.c27 static inline mem_addr_t get_lock_addr(const struct device *dev, uint32_t id) in get_lock_addr() argument
29 return (mem_addr_t)(DEVICE_MMIO_GET(dev) + id * sizeof(uint32_t)); in get_lock_addr()
43 static int sqn_hwspinlock_trylock(const struct device *dev, uint32_t id) in sqn_hwspinlock_trylock() argument
48 if (id > config->num_locks) { in sqn_hwspinlock_trylock()
60 if (sys_read8(get_lock_addr(dev, id)) == cpuid) { in sqn_hwspinlock_trylock()
64 sys_write8(cpuid, get_lock_addr(dev, id)); in sqn_hwspinlock_trylock()
65 if (sys_read8(get_lock_addr(dev, id)) == cpuid) { in sqn_hwspinlock_trylock()
72 static void sqn_hwspinlock_lock(const struct device *dev, uint32_t id) in sqn_hwspinlock_lock() argument
77 if (id > config->num_locks) { in sqn_hwspinlock_lock()
78 LOG_ERR("unsupported hwspinlock id '%d'", id); in sqn_hwspinlock_lock()
[all …]
/Zephyr-latest/drivers/display/
Ddisplay_renesas_ra.c275 #define IRQ_CONFIGURE_FUNC(id) \ argument
276 static void glcdc_renesas_ra_configure_func_##id(void) \
278 R_ICU->IELSR[DT_INST_IRQ_BY_NAME(id, line, irq)] = ELC_EVENT_GLCDC_LINE_DETECT; \
279 IRQ_CONNECT(DT_INST_IRQ_BY_NAME(id, line, irq), \
280 DT_INST_IRQ_BY_NAME(id, line, priority), renesas_ra_glcdc_isr, \
281 DEVICE_DT_INST_GET(id), 0); \
282 irq_enable(DT_INST_IRQ_BY_NAME(id, line, irq)); \
285 #define IRQ_CONFIGURE_DEFINE(id) .irq_configure = glcdc_renesas_ra_configure_func_##id argument
287 #define RENESAS_RA_FRAME_BUFFER_LEN(id) \ argument
288 (BYTE_PER_PIXEL * DT_INST_PROP(id, height) * DT_INST_PROP(id, width))
[all …]
/Zephyr-latest/tests/drivers/can/api/src/
Dcommon.c30 .id = TEST_CAN_STD_ID_1,
40 .id = TEST_CAN_STD_ID_2,
50 .id = TEST_CAN_EXT_ID_1,
60 .id = TEST_CAN_EXT_ID_2,
70 .id = TEST_CAN_STD_ID_1,
80 .id = TEST_CAN_EXT_ID_1,
91 .id = TEST_CAN_STD_ID_1,
105 .id = TEST_CAN_STD_ID_2,
121 .id = TEST_CAN_STD_ID_1,
131 .id = TEST_CAN_STD_ID_2,
[all …]
/Zephyr-latest/drivers/mbox/
Dmbox_nrf_vevif_event_rx.c37 uint8_t id) in trigger_callback() argument
39 uint8_t idx = id - EVENTS_IDX_MIN; in trigger_callback()
41 if ((cbs->enabled_mask & BIT(id)) && (cbs->cb[idx] != NULL)) { in trigger_callback()
42 cbs->cb[idx](dev, id, cbs->user_data[idx], NULL); in trigger_callback()
54 for (uint8_t id = EVENTS_IDX_MIN; id < EVENTS_IDX_MAX + 1U; id++) { in vevif_event_rx_isr() local
55 nrf_vpr_event_t event = nrfy_vpr_triggered_event_get(id); in vevif_event_rx_isr()
58 trigger_callback(dev, cbs, id); in vevif_event_rx_isr()
66 static inline bool vevif_event_rx_event_is_valid(uint32_t events_mask, uint32_t id) in vevif_event_rx_event_is_valid() argument
68 return ((id <= EVENTS_IDX_MAX) && ((events_mask & BIT(id)) != 0U)); in vevif_event_rx_event_is_valid()
78 static int vevif_event_rx_register_callback(const struct device *dev, uint32_t id, in vevif_event_rx_register_callback() argument
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