70 static void dma_stm32_dump_stream_irq(const struct device *dev, uint32_t id)  in dma_stm32_dump_stream_irq()  argument
75 	stm32_dma_dump_stream_irq(dma, id);  in dma_stm32_dump_stream_irq()
78 static void dma_stm32_clear_stream_irq(const struct device *dev, uint32_t id)  in dma_stm32_clear_stream_irq()  argument
83 	dma_stm32_clear_tc(dma, id);  in dma_stm32_clear_stream_irq()
84 	dma_stm32_clear_ht(dma, id);  in dma_stm32_clear_stream_irq()
85 	stm32_dma_clear_stream_irq(dma, id);  in dma_stm32_clear_stream_irq()
88 static void dma_stm32_irq_handler(const struct device *dev, uint32_t id)  in dma_stm32_irq_handler()  argument
95 	__ASSERT_NO_MSG(id < config->max_streams);  in dma_stm32_irq_handler()
97 	stream = &config->streams[id];  in dma_stm32_irq_handler()
105 		dma_stm32_clear_stream_irq(dev, id);  in dma_stm32_irq_handler()
111 	callback_arg = id + STM32_DMA_STREAM_OFFSET;  in dma_stm32_irq_handler()
115 	if (stm32_dma_is_ht_irq_active(dma, id)) {  in dma_stm32_irq_handler()
118 			dma_stm32_clear_ht(dma, id);  in dma_stm32_irq_handler()
121 	} else if (stm32_dma_is_tc_irq_active(dma, id)) {  in dma_stm32_irq_handler()
128 			dma_stm32_clear_tc(dma, id);  in dma_stm32_irq_handler()
131 	} else if (stm32_dma_is_unexpected_irq_happened(dma, id)) {  in dma_stm32_irq_handler()
138 		dma_stm32_dump_stream_irq(dev, id);  in dma_stm32_irq_handler()
139 		dma_stm32_clear_stream_irq(dev, id);  in dma_stm32_irq_handler()
153 	for (id = 0; id < cfg_##index->max_streams; ++id) {		       \
154 		if (stm32_dma_is_irq_active(dma_##index, id)) {		       \
155 			dma_stm32_irq_handler(dev_##index, id);		       \
162 	uint32_t id = 0;  in dma_stm32_shared_irq_handler()  local
253 static int dma_stm32_disable_stream(DMA_TypeDef *dma, uint32_t id)  in dma_stm32_disable_stream()  argument
258 		if (stm32_dma_disable_stream(dma, id) == 0) {  in dma_stm32_disable_stream()
272 					     uint32_t id,  in dma_stm32_configure()  argument
277 				&dev_config->streams[id - STM32_DMA_STREAM_OFFSET];  in dma_stm32_configure()
285 	id = id - STM32_DMA_STREAM_OFFSET;  in dma_stm32_configure()
287 	if (id >= dev_config->max_streams) {  in dma_stm32_configure()
288 		LOG_ERR("cannot configure the dma stream %d.", id);  in dma_stm32_configure()
293 		LOG_ERR("dma stream %d is busy.", id);  in dma_stm32_configure()
297 	if (dma_stm32_disable_stream(dma, id) != 0) {  in dma_stm32_configure()
298 		LOG_ERR("could not disable dma stream %d.", id);  in dma_stm32_configure()
302 	dma_stm32_clear_stream_irq(dev, id);  in dma_stm32_configure()
425 				id, DMA_InitStruct.MemoryOrM2MDstIncMode);  in dma_stm32_configure()
434 				id, DMA_InitStruct.PeriphOrM2MSrcIncMode);  in dma_stm32_configure()
493 	LL_DMA_Init(dma, dma_stm32_id_to_stream(id), &DMA_InitStruct);  in dma_stm32_configure()
495 	LL_DMA_EnableIT_TC(dma, dma_stm32_id_to_stream(id));  in dma_stm32_configure()
499 		LL_DMA_EnableIT_HT(dma, dma_stm32_id_to_stream(id));  in dma_stm32_configure()
504 		LL_DMA_EnableFifoMode(dma, dma_stm32_id_to_stream(id));  in dma_stm32_configure()
505 		LL_DMA_EnableIT_FE(dma, dma_stm32_id_to_stream(id));  in dma_stm32_configure()
507 		LL_DMA_DisableFifoMode(dma, dma_stm32_id_to_stream(id));  in dma_stm32_configure()
508 		LL_DMA_DisableIT_FE(dma, dma_stm32_id_to_stream(id));  in dma_stm32_configure()
514 DMA_STM32_EXPORT_API int dma_stm32_reload(const struct device *dev, uint32_t id,  in dma_stm32_reload()  argument
523 	id = id - STM32_DMA_STREAM_OFFSET;  in dma_stm32_reload()
525 	if (id >= config->max_streams) {  in dma_stm32_reload()
529 	stream = &config->streams[id];  in dma_stm32_reload()
531 	if (dma_stm32_disable_stream(dma, id) != 0) {  in dma_stm32_reload()
537 		LL_DMA_SetMemoryAddress(dma, dma_stm32_id_to_stream(id), src);  in dma_stm32_reload()
538 		LL_DMA_SetPeriphAddress(dma, dma_stm32_id_to_stream(id), dst);  in dma_stm32_reload()
542 		LL_DMA_SetPeriphAddress(dma, dma_stm32_id_to_stream(id), src);  in dma_stm32_reload()
543 		LL_DMA_SetMemoryAddress(dma, dma_stm32_id_to_stream(id), dst);  in dma_stm32_reload()
550 		LL_DMA_SetDataLength(dma, dma_stm32_id_to_stream(id),  in dma_stm32_reload()
553 		LL_DMA_SetDataLength(dma, dma_stm32_id_to_stream(id),  in dma_stm32_reload()
560 	stm32_dma_enable_stream(dma, id);  in dma_stm32_reload()
565 DMA_STM32_EXPORT_API int dma_stm32_start(const struct device *dev, uint32_t id)  in dma_stm32_start()  argument
572 	id = id - STM32_DMA_STREAM_OFFSET;  in dma_stm32_start()
575 	if (id >= config->max_streams) {  in dma_stm32_start()
580 	if (stm32_dma_is_enabled_stream(dma, id)) {  in dma_stm32_start()
585 	stream = &config->streams[id];  in dma_stm32_start()
588 	dma_stm32_clear_stream_irq(dev, id);  in dma_stm32_start()
589 	stm32_dma_enable_stream(dma, id);  in dma_stm32_start()
594 DMA_STM32_EXPORT_API int dma_stm32_stop(const struct device *dev, uint32_t id)  in dma_stm32_stop()  argument
597 	struct dma_stm32_stream *stream = &config->streams[id - STM32_DMA_STREAM_OFFSET];  in dma_stm32_stop()
601 	id = id - STM32_DMA_STREAM_OFFSET;  in dma_stm32_stop()
603 	if (id >= config->max_streams) {  in dma_stm32_stop()
613 	if (!stm32_dma_is_enabled_stream(dma, id)) {  in dma_stm32_stop()
619 	LL_DMA_DisableIT_TC(dma, dma_stm32_id_to_stream(id));  in dma_stm32_stop()
623 	stm32_dma_disable_fifo_irq(dma, id);  in dma_stm32_stop()
626 	dma_stm32_clear_stream_irq(dev, id);  in dma_stm32_stop()
627 	dma_stm32_disable_stream(dma, id);  in dma_stm32_stop()
669 				uint32_t id, struct dma_status *stat)  in dma_stm32_get_status()  argument
676 	id = id - STM32_DMA_STREAM_OFFSET;  in dma_stm32_get_status()
677 	if (id >= config->max_streams) {  in dma_stm32_get_status()
681 	stream = &config->streams[id];  in dma_stm32_get_status()
682 	stat->pending_length = LL_DMA_GetDataLength(dma, dma_stm32_id_to_stream(id));  in dma_stm32_get_status()