Searched refs:well (Results 126 – 150 of 401) sorted by relevance
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| /Zephyr-latest/boards/renesas/ek_ra6m4/doc/ |
| D | index.rst | 9 BOM cost, as well as the integrated Ethernet MAC with individual DMA
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| /Zephyr-latest/boards/st/nucleo_f413zh/doc/ |
| D | index.rst | 107 as well as main PLL clock. By default System clock is driven by PLL clock at 96MHz,
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| /Zephyr-latest/boards/st/nucleo_g431kb/doc/ |
| D | index.rst | 59 as well as main PLL clock. By default the external oscillator is not connected to the board. Theref…
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| /Zephyr-latest/tests/bsim/bluetooth/mesh/ |
| D | README.rst | 83 mesh initialization, as well as message sending and receiving.
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| /Zephyr-latest/samples/net/sockets/echo_server/ |
| D | README.rst | 137 You can verify TLS communication with a Linux host as well. See
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| /Zephyr-latest/subsys/settings/ |
| D | Kconfig | 171 The maximum number of hash collisions needs to be well sized depending
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| /Zephyr-latest/doc/develop/tools/ |
| D | stm32cubeide.rst | 87 The project can be run using the :guilabel:`Run` button, as well as debugged
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| /Zephyr-latest/samples/subsys/llext/edk/ |
| D | README.rst | 34 the Zephyr build system as well, via ``llext-edk`` target. The EDK is then
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| /Zephyr-latest/cmake/modules/ |
| D | boards.cmake | 7 # This CMake module will validate the BOARD argument as well as splitting the
152 # This command is used for locating the board dir as well as printing all boards
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| /Zephyr-latest/doc/connectivity/networking/api/ |
| D | net_l2.rst | 116 here as well. There are two specific differences however:
161 as well as other hardware-related configuration to L2. Similarly, drivers may
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| /Zephyr-latest/doc/build/dts/ |
| D | bindings-upstream.rst | 101 this rule is if you are replicating a well-established binding from somewhere
113 If your binding describes hardware with a well known vendor from the list in
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| /Zephyr-latest/boards/raspberrypi/rpi_pico/doc/ |
| D | index.rst | 106 combination of GPIO pins for an SPI bus, as well as allowing up to
108 devices as well as both PIO devices).
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| /Zephyr-latest/doc/ |
| D | glossary.rst | 133 as well as peripherals and memory.
186 as well as that of its :term:`west projects <west project>` onto your
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| /Zephyr-latest/boards/snps/nsim/arc_classic/doc/ |
| D | index.rst | 81 MetaWare Debugger from `ARC MWDT`_ is required as well as the HAPS platform itself.
148 as well as flash proper built FPGA image (aka .bit-file). This instruction doesn't cover those
181 The ``west debug`` (as well as ``west flash``) is just a wrapper script and so it's possible to
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| /Zephyr-latest/doc/security/ |
| D | sensor-threat.rst | 8 be used to help prioritize these efforts as well.
14 to send configuration data to the device, as well as software update
152 application image as well as updating the application image from
312 data, as well as the cloud service data associated with the
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| /Zephyr-latest/doc/develop/flash_debug/ |
| D | probes.rst | 149 as well as a USB-Serial adapter. It is compatible with the following debug host
193 including IAR EWARM, Keil MDK, as well as NXP’s MCUXpresso IDE and
195 As well as providing debug probe functionality, the LPC-Link2 probes also
231 as well as a USB-Serial adapter. It is compatible with the following debug host
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| /Zephyr-latest/boards/phytec/phyboard_nash/doc/ |
| D | index.rst | 17 well as the Cortex-M33 core.
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| /Zephyr-latest/boards/fanke/fk7b0m1_vbt6/doc/ |
| D | index.rst | 119 as well as by the main PLL clock. By default the system clock is driven by the PLL clock at 280MHz,
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| /Zephyr-latest/boards/96boards/carbon/doc/ |
| D | nrf51822.rst | 102 ARM Embedded, can be used as well.
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| /Zephyr-latest/boards/st/stm32f072b_disco/doc/ |
| D | index.rst | 98 oscillator, as well as main PLL clock. By default System clock is driven
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| /Zephyr-latest/boards/st/stm32f413h_disco/doc/ |
| D | index.rst | 99 as well as main PLL clock. By default System clock is driven by PLL clock at 100MHz,
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| /Zephyr-latest/boards/96boards/stm32_sensor_mez/doc/ |
| D | index.rst | 99 well as the main PLL clock. In default board configuration, the 16MHz external
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| /Zephyr-latest/boards/96boards/wistrio/doc/ |
| D | 96b_wistrio.rst | 169 ARM Embedded, can be used as well.
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| /Zephyr-latest/boards/st/stm32f412g_disco/doc/ |
| D | index.rst | 98 as well as main PLL clock. By default System clock is driven by PLL clock at 100MHz,
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| /Zephyr-latest/boards/st/stm32f469i_disco/doc/ |
| D | index.rst | 104 as well as main PLL clock. By default System clock is driven by PLL clock at 180MHz,
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