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Searched refs:sys_read32 (Results 101 – 125 of 196) sorted by relevance

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/Zephyr-latest/drivers/spi/
Dspi_ambiq_bleif.c153 if (!sys_read32(SPI_STAT(dev))) { in spi_ambiq_release()
204 sys_write32((sys_read32(addr) | DT_INST_PHA(n, ambiq_pwrcfg, mask)), addr); \
/Zephyr-latest/drivers/pinctrl/
Dpinctrl_emsdp.c117 reg = sys_read32(mux_regs + PMOD_MUX_CTRL); in pinctrl_emsdp_set()
119 reg = sys_read32(mux_regs + ARDUINO_MUX_CTRL); in pinctrl_emsdp_set()
/Zephyr-latest/drivers/i2s/
Di2s_litex.c176 *(dst + i) = sys_read32(I2S_RX_FIFO_ADDR); in i2s_copy_from_fifo()
180 data = sys_read32(I2S_RX_FIFO_ADDR); in i2s_copy_from_fifo()
188 data = sys_read32(I2S_RX_FIFO_ADDR); in i2s_copy_from_fifo()
201 sys_read32(I2S_RX_FIFO_ADDR); in i2s_copy_from_fifo()
533 sys_read32(I2S_RX_FIFO_ADDR); in clear_rx_fifo()
/Zephyr-latest/drivers/ethernet/
Dphy_xlnx_gem.c56 reg_val = sys_read32(base_addr + ETH_XLNX_GEM_NWSR_OFFSET); in phy_xlnx_gem_mdio_read()
89 reg_val = sys_read32(base_addr + ETH_XLNX_GEM_NWSR_OFFSET); in phy_xlnx_gem_mdio_read()
102 reg_val = sys_read32(base_addr + ETH_XLNX_GEM_PHY_MAINTENANCE_OFFSET); in phy_xlnx_gem_mdio_read()
135 reg_val = sys_read32(base_addr + ETH_XLNX_GEM_NWSR_OFFSET); in phy_xlnx_gem_mdio_write()
170 reg_val = sys_read32(base_addr + ETH_XLNX_GEM_NWSR_OFFSET); in phy_xlnx_gem_mdio_write()
Deth_e1000_priv.h113 uint32_t val = sys_read32((_dev)->address + (_reg)); \
/Zephyr-latest/drivers/counter/
Dcounter_dw_timer.c93 sys_read32(reg_base + EOI_OFST); in counter_dw_timer_irq_handler()
147 top_val = sys_read32(reg_base + LOADCOUNT_OFST); in counter_dw_timer_get_top_value()
157 *ticks = sys_read32(reg_base + CURRENTVAL_OFST); in counter_dw_timer_get_value()
/Zephyr-latest/include/zephyr/drivers/interrupt_controller/
Dloapic.h89 return sys_read32(base + reg); in x86_read_xapic()
/Zephyr-latest/drivers/pinctrl/renesas/rz/
Dpinctrl_rzt2m.c37 uint32_t pfc = sys_read32(PFC(pin->port)) & ~(PFC_FUNC_MASK(pin->pin)); in pinctrl_configure_pin()
/Zephyr-latest/drivers/entropy/
Dentropy_cc13xx_cc26xx.c45 while (sys_read32(TRNG_BASE + TRNG_O_SWRESET)) { in start_trng()
83 off = sys_read32(TRNG_BASE + TRNG_O_ALARMSTOP); in handle_shutdown_ovf()
Dentropy_neorv32_trng.c34 return sys_read32(config->base); in neorv32_trng_read_ctrl()
/Zephyr-latest/drivers/can/
Dcan_nrf.c41 if (sys_read32(config->wrapper + CAN_EVENTS_CORE_0) == 1U) { in can_nrf_irq_handler()
46 if (sys_read32(config->wrapper + CAN_EVENTS_CORE_1) == 1U) { in can_nrf_irq_handler()
/Zephyr-latest/drivers/clock_control/
Dclock_control_r8a779f0_cpg_mssr.c90 reg = sys_read32(DEVICE_MMIO_GET(dev) + clk_info->offset); in r8a779f0_cpg_enable_disable_core()
95 reg = sys_read32(DEVICE_MMIO_GET(dev) + clk_info->offset); in r8a779f0_cpg_enable_disable_core()
Dclock_control_renesas_cpg_mssr.c43 reg_val = sys_read32(base_address + mstpcr[reg]); in rcar_cpg_mstp_clock_endisable()
108 reg_val = sys_read32(reg_addr); in rcar_cpg_get_divider()
316 uint32_t reg = sys_read32(clk_info->offset + DEVICE_MMIO_GET(dev)); in rcar_cpg_set_rate()
Dclock_agilex_ll.c20 #define mmio_read_32(addr) sys_read32((addr))
/Zephyr-latest/drivers/dai/intel/dmic/
Ddmic_nhlt.c34 return sys_read32(dmic->reg_base + reg); in dai_dmic_read()
286 val = sys_read32(dmic->vshim_base + DMICLVSCTL_OFFSET); in dai_dmic_clock_select_set()
291 val = sys_read32(dmic->shim_base + DMICLCTL_OFFSET); in dai_dmic_clock_select_set()
307 val = sys_read32(dmic->vshim_base + DMICLVSCTL_OFFSET); in dai_dmic_clock_select_get()
310 val = sys_read32(dmic->shim_base + DMICLCTL_OFFSET); in dai_dmic_clock_select_get()
329 if (clock_source && !(sys_read32(dmic->shim_base + DMICLCAP_OFFSET) & DMICLCAP_MLCS)) { in dai_dmic_set_clock()
/Zephyr-latest/drivers/usb/udc/
Dudc_rpi_pico.c144 return sys_read32(buf_ctrl_reg); in read_buf_ctrl_reg()
181 while ((sys_read32(abort_done_reg) & ep_mask) != ep_mask) { in rpi_pico_ep_cancel()
485 sys_put_le32(sys_read32((uintptr_t)&dpram->setup_packet[0]), &priv->setup[0]); in rpi_pico_handle_setup()
486 sys_put_le32(sys_read32((uintptr_t)&dpram->setup_packet[4]), &priv->setup[4]); in rpi_pico_handle_setup()
569 buf_status = sys_read32((mm_reg_t)&base->buf_status); in rpi_pico_handle_buff_status()
600 sys_read32((mm_reg_t)&base->sof_rd); in rpi_pico_isr_handler()
609 sie_status = sys_read32((mm_reg_t)&base->sie_status); in rpi_pico_isr_handler()
866 cfg->addr, sys_read32(buf_ctrl_reg)); in udc_rpi_pico_ep_clear_halt()
/Zephyr-latest/arch/x86/core/
Dearly_serial.c28 #define IN(reg) (sys_read32(mmio + (reg) * 4) & 0xff)
/Zephyr-latest/drivers/gpio/
Dgpio_rp1.c128 *value = sys_read32(RIO_IN(data->rio_base)); in gpio_rp1_port_get_raw()
172 val = sys_read32(RIO_OUT(data->rio_base)); in gpio_rp1_port_toggle_bits()
/Zephyr-latest/drivers/syscon/
Dsyscon.c71 *val = sys_read32(base_address + reg); in syscon_generic_read_reg()
/Zephyr-latest/drivers/reset/
Dreset_intel_socfpga.c36 value = sys_read32(base_address + offset); in reset_intel_soc_status()
/Zephyr-latest/subsys/shell/modules/
Ddevmem_service.c76 value = sys_le32_to_cpu(sys_read32(addr + data_offset)); in memory_dump()
271 value = sys_read32(addr); in memory_read()
/Zephyr-latest/soc/nxp/s32/common/
Dmc_rgm.c60 #define REG_READ(r) sys_read32((mem_addr_t)(DT_INST_REG_ADDR(0) + (r)))
/Zephyr-latest/drivers/interrupt_controller/
Dintc_plic.c250 return sys_read32(trig_addr) & GENMASK(offset + CONFIG_PLIC_TRIG_TYPE_BITWIDTH - 1, offset); in riscv_plic_irq_trig_val()
264 en_value = sys_read32(en_addr); in plic_irq_enable_set_state()
322 uint32_t en_value = sys_read32(en_addr); in local_irq_is_enabled()
386 uint32_t pend_value = sys_read32(pend_addr); in riscv_plic_irq_set_pending()
503 const uint32_t local_irq = sys_read32(claim_complete_addr); in plic_irq_handler()
/Zephyr-latest/drivers/watchdog/
Dwdt_andes_atcwdt200.c156 reg = sys_read32(WDT_CTRL(wdt_addr)); in wdt_atcwdt200_disable()
185 reg = sys_read32(WDT_CTRL(wdt_addr)); in wdt_atcwdt200_setup()
/Zephyr-latest/tests/subsys/edac/ibecc/src/
Dibecc.c206 test_value = sys_read32(test_addr); in test_inject()
214 test_value = sys_read32(test_addr); in test_inject()

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