Searched refs:riscv (Results 76 – 100 of 117) sorted by relevance
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| /Zephyr-latest/cmake/toolchain/llvm/ |
| D | target.cmake | 36 elseif("${ARCH}" STREQUAL "riscv")
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| /Zephyr-latest/dts/riscv/ |
| D | riscv32-litex-vexriscv.dtsi | 25 compatible = "litex,vexriscv-standard", "riscv";
28 riscv,isa = "rv32im_zicsr_zifencei";
53 riscv,max-priority = <7>;
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| /Zephyr-latest/dts/riscv/gd/ |
| D | gd32vf103.dtsi | 26 compatible = "nuclei,bumblebee", "riscv";
27 riscv,isa = "rv32imac_zicsr_zifencei";
44 compatible = "nuclei,systimer", "riscv,machine-timer";
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| /Zephyr-latest/dts/riscv/espressif/esp32c6/ |
| D | esp32c6_common.dtsi | 30 compatible = "espressif,riscv";
31 riscv,isa = "rv32imac_zicsr";
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| /Zephyr-latest/dts/riscv/openisa/ |
| D | rv32m1_zero_riscy.dtsi | 6 #include <riscv/openisa/rv32m1.dtsi>
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| D | rv32m1_ri5cy.dtsi | 6 #include <riscv/openisa/rv32m1.dtsi>
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| /Zephyr-latest/soc/espressif/esp32c2/ |
| D | mcuboot.ld | 270 SECTION_PROLOGUE(.riscv.attributes, 0,)
272 KEEP(*(.riscv.attributes))
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| D | default.ld | 795 SECTION_PROLOGUE(.riscv.attributes, 0,)
797 KEEP(*(.riscv.attributes))
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| /Zephyr-latest/soc/espressif/esp32c3/ |
| D | mcuboot.ld | 270 SECTION_PROLOGUE(.riscv.attributes, 0,)
272 KEEP(*(.riscv.attributes))
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| /Zephyr-latest/soc/espressif/esp32c6/ |
| D | mcuboot.ld | 270 SECTION_PROLOGUE(.riscv.attributes, 0,)
272 KEEP(*(.riscv.attributes))
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| /Zephyr-latest/boards/beagle/beaglev_fire/doc/ |
| D | index.rst | 60 <softconsole_path>/openocd/share/openocd/scripts/board/microsemi-riscv.cfg
78 set arch riscv:rv64
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| /Zephyr-latest/include/zephyr/arch/riscv/common/ |
| D | linker.ld | 11 * Generic Linker script for the riscv platform
431 SECTION_PROLOGUE(.riscv.attributes, 0,)
433 KEEP(*(.riscv.attributes))
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| /Zephyr-latest/boards/gd/gd32vf103c_starter/doc/ |
| D | index.rst | 109 https://github.com/riscv-mcu/GD32VF103_Demo_Suites/tree/master/GD32VF103C_START_Demo_Suites/Docs
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| /Zephyr-latest/boards/gd/gd32vf103v_eval/doc/ |
| D | index.rst | 116 https://github.com/riscv-mcu/GD32VF103_Demo_Suites/tree/master/GD32VF103V_EVAL_Demo_Suites/Docs
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| /Zephyr-latest/cmake/compiler/clang/ |
| D | target.cmake | 36 elseif("${ARCH}" STREQUAL "riscv")
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| /Zephyr-latest/dts/riscv/ite/ |
| D | it8xxx2.dtsi | 31 compatible = "ite,riscv-ite", "riscv";
32 riscv,isa = "rv32imafc_zifencei";
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| /Zephyr-latest/soc/andestech/ae350/ |
| D | linker.ld | 402 SECTION_PROLOGUE(.riscv.attributes, 0,)
404 KEEP(*(.riscv.attributes))
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| /Zephyr-latest/cmake/compiler/gcc/ |
| D | target.cmake | 72 elseif("${ARCH}" STREQUAL "riscv")
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| /Zephyr-latest/dts/bindings/ |
| D | binding-types.txt | 106 riscv RISC-V architecture
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| /Zephyr-latest/boards/openisa/rv32m1_vega/doc/ |
| D | index.rst | 664 - Base toolchain: `pulp-riscv-gnu-toolchain`_; extra toolchain patches:
704 The build toolchain is based on the `pulp-riscv-gnu-toolchain`_, with
740 https://github.com/pulp-platform/riscv
746 .. _pulp-riscv-gnu-toolchain:
747 https://github.com/pulp-platform/pulp-riscv-gnu-toolchain
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| /Zephyr-latest/soc/ite/ec/it8xxx2/ |
| D | linker.ld | 478 SECTION_PROLOGUE(.riscv.attributes, 0,)
480 KEEP(*(.riscv.attributes))
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| /Zephyr-latest/boards/lilygo/ttgo_t8c3/doc/ |
| D | index.rst | 32 | PMP | on-chip | arch/riscv |
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| /Zephyr-latest/boards/enjoydigital/litex_vexriscv/doc/ |
| D | index.rst | 134 ./litex_setup.py --gcc=riscv
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| /Zephyr-latest/arch/riscv/ |
| D | Kconfig | 10 default "riscv"
262 Allow SOCs that have custom extended riscv ISA to still
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| /Zephyr-latest/doc/releases/ |
| D | release-notes-3.5.rst | 1022 * The ``riscv,isa`` property used by RISC-V CPU bindings no longer has an
1028 * new property: ``riscv,isa``
1250 * :dtcompatible:`espressif,riscv`:
1253 * new property: ``riscv,isa``
1336 * new property: ``riscv,isa``
1378 * :dtcompatible:`ite,riscv-ite`:
1381 * new property: ``riscv,isa``
1509 * new property: ``riscv,isa``
1879 * new property: ``riscv,isa``
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