Searched refs:riscv (Results 51 – 75 of 117) sorted by relevance
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| /Zephyr-latest/arch/mips/ |
| D | CMakeLists.txt | 4 # based on arch/riscv/CMakeLists.txt
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| D | Kconfig | 4 # based on arch/riscv/Kconfig
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| /Zephyr-latest/soc/gd/gd32/gd32vf103/ |
| D | CMakeLists.txt | 12 set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/riscv/common/linker.ld CACHE INTERNAL "")
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| /Zephyr-latest/soc/snps/nsim/arc_v/rmx/ |
| D | CMakeLists.txt | 12 set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/riscv/common/linker.ld CACHE INTERNAL "")
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| /Zephyr-latest/soc/sensry/ganymed/sy1xx/common/ |
| D | linker.ld | 10 * - include/arch/riscv/common/linker.ld
11 * - include/arch/riscv/pulpino/linker.ld
161 /* https://groups.google.com/a/groups.riscv.org/d/msg/sw-dev/60IdaZj27dY/TKT3hbNlAgAJ */
243 SECTION_PROLOGUE(.riscv.attributes, 0,)
245 KEEP(*(.riscv.attributes))
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| /Zephyr-latest/tests/drivers/build_all/gpio/ |
| D | altera.overlay | 16 compatible = "riscv,cpu-intc";
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| /Zephyr-latest/soc/openisa/rv32m1/ |
| D | linker.ld | 9 * - include/arch/riscv/common/linker.ld
10 * - include/arch/riscv/pulpino/linker.ld
180 /* https://groups.google.com/a/groups.riscv.org/d/msg/sw-dev/60IdaZj27dY/TKT3hbNlAgAJ */
260 SECTION_PROLOGUE(.riscv.attributes, 0,)
262 KEEP(*(.riscv.attributes))
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| /Zephyr-latest/dts/riscv/wch/ |
| D | qingke-v2.dtsi | 19 riscv,isa = "rv32ec_zicsr_zifencei";
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| D | qingke-v4c.dtsi | 19 riscv,isa = "rv32imac_zicsr_zifencei";
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| /Zephyr-latest/arch/common/ |
| D | Kconfig | 15 https://github.com/riscv/riscv-semihosting-spec/blob/main/riscv-semihosting-spec.adoc
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| /Zephyr-latest/tests/application_development/code_relocation/ |
| D | linker_riscv_qemu_sram2.ld | 27 #include <zephyr/arch/riscv/common/linker.ld>
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| /Zephyr-latest/boards/others/neorv32/support/ |
| D | neorv32.cfg | 32 target create $_TARGETNAME.0 riscv -chain-position $_TARGETNAME
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| /Zephyr-latest/soc/telink/tlsr/tlsr951x/ |
| D | linker.ld | 19 #include <zephyr/arch/riscv/common/linker.ld>
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| /Zephyr-latest/dts/riscv/espressif/esp32c2/ |
| D | esp32c2_common.dtsi | 34 compatible = "espressif,riscv", "riscv";
35 riscv,isa = "rv32imc_zicsr";
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| /Zephyr-latest/boards/others/neorv32/ |
| D | neorv32.dts | 57 riscv,isa = "rv32im_zicsr_zifencei";
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| /Zephyr-latest/dts/riscv/sensry/ |
| D | ganymed-sy1xx.dtsi | 21 compatible = "sensry,sy1xx", "riscv";
23 riscv,isa = "rv32imc_zicsr";
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| /Zephyr-latest/boards/sifive/hifive1/doc/ |
| D | index.rst | 63 ``-DOPENOCD=<path/to/riscv-openocd/bin/openocd>`` parameter when building:
68 :gen-args: -DOPENOCD=<path/to/riscv-openocd/bin/openocd>
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| /Zephyr-latest/modules/hal_gigadevice/ |
| D | CMakeLists.txt | 12 set(gd32_soc_sys_dir ${gd32_soc_dir}/riscv)
13 zephyr_include_directories(${gd32_soc_dir}/riscv/drivers)
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| /Zephyr-latest/samples/drivers/clock_control_litex/ |
| D | README.rst | 23 .. literalinclude:: ../../../dts/riscv/riscv32-litex-vexriscv.dtsi
29 .. literalinclude:: ../../../dts/riscv/riscv32-litex-vexriscv.dtsi
35 .. literalinclude:: ../../../dts/riscv/riscv32-litex-vexriscv.dtsi
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| /Zephyr-latest/boards/sifive/hifive_unleashed/doc/ |
| D | index.rst | 45 -f boards/riscv/hifive_unleashed/support/openocd_hifive_unleashed.cfg
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| /Zephyr-latest/boards/sifive/hifive_unmatched/doc/ |
| D | index.rst | 45 -f boards/riscv/hifive_unmatched/support/openocd_hifive_unmatched.cfg
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| /Zephyr-latest/cmake/toolchain/iar/ |
| D | generic.cmake | 42 set(SYSROOT_TARGET riscv)
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| /Zephyr-latest/doc/hardware/arch/ |
| D | risc-v.rst | 27 kconfig. Look at :file:`arch/riscv/Kconfig.isa` for more information.
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| /Zephyr-latest/dts/riscv/espressif/esp32c3/ |
| D | esp32c3_common.dtsi | 36 compatible = "espressif,riscv", "riscv";
37 riscv,isa = "rv32imc_zicsr";
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| /Zephyr-latest/dts/riscv/openisa/ |
| D | rv32m1.dtsi | 25 compatible = "openisa,ri5cy", "riscv";
26 riscv,isa = "rv32imc_zicsr_zifencei";
32 compatible = "openisa,zero-ri5cy", "riscv";
33 riscv,isa = "rv32imc_zicsr_zifencei";
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