| /Zephyr-latest/soc/microchip/mec/mec172x/ |
| D | soc_power_debug.h | 24 struct gpio_regs * const regs = in pm_dp_gpio() local
27 regs->CTRL[DP_GPIO_ID] = gpio_ctrl_val; in pm_dp_gpio()
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| /Zephyr-latest/drivers/counter/ |
| D | counter_sam_tc.c | 52 Tc *regs; member
102 Tc *tc = dev_cfg->regs; in counter_sam_tc_start()
113 Tc *tc = dev_cfg->regs; in counter_sam_tc_stop()
124 Tc *tc = dev_cfg->regs; in counter_sam_tc_get_value()
137 Tc *tc = dev_cfg->regs; in counter_sam_tc_set_alarm()
199 Tc *tc = dev_cfg->regs; in counter_sam_tc_cancel_alarm()
223 Tc *tc = dev_cfg->regs; in counter_sam_tc_set_top_value()
261 Tc *tc = dev_cfg->regs; in counter_sam_tc_get_top_value()
270 Tc *tc = dev_cfg->regs; in counter_sam_tc_get_pending_int()
280 Tc *tc = dev_cfg->regs; in counter_sam_tc_isr()
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| /Zephyr-latest/drivers/virtualization/ |
| D | virt_ivshmem.c | 197 volatile struct ivshmem_v2_reg *regs = in ivshmem_configure() local
200 data->max_peers = regs->max_peers; in ivshmem_configure()
250 if (i == regs->id) { in ivshmem_configure()
331 volatile struct ivshmem_v2_reg *regs = in ivshmem_api_get_id() local
334 id = regs->id; in ivshmem_api_get_id()
338 volatile struct ivshmem_reg *regs = in ivshmem_api_get_id() local
341 id = regs->iv_position; in ivshmem_api_get_id()
376 volatile struct ivshmem_v2_reg *regs = in ivshmem_api_int_peer() local
379 doorbell_reg = ®s->doorbell; in ivshmem_api_int_peer()
383 volatile struct ivshmem_reg *regs = in ivshmem_api_int_peer() local
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| /Zephyr-latest/drivers/sensor/qdec_sam/ |
| D | qdec_sam.c | 28 Tc *regs; member
42 Tc *const tc = dev_cfg->regs; in qdec_sam_fetch()
78 Tc *const tc = dev_cfg->regs; in qdec_sam_configure()
128 .regs = (Tc *)DT_REG_ADDR(DT_INST_PARENT(n)), \
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| /Zephyr-latest/tests/drivers/flash/stm32/src/ |
| D | main.c | 194 FLASH_TypeDef *regs = (FLASH_TypeDef *)TEST_AREA_DEVICE_REG; in flash_opt_locked() local
196 return regs->OPTCR & FLASH_OPTCR_OPTLOCK; in flash_opt_locked()
201 FLASH_TypeDef *regs = (FLASH_TypeDef *)TEST_AREA_DEVICE_REG; in flash_cr_unlock() local
203 regs->KEYR = FLASH_KEY1; in flash_cr_unlock()
204 regs->KEYR = FLASH_KEY2; in flash_cr_unlock()
209 FLASH_TypeDef *regs = (FLASH_TypeDef *)TEST_AREA_DEVICE_REG; in flash_cr_locked() local
211 return regs->CR & FLASH_CR_LOCK; in flash_cr_locked()
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| /Zephyr-latest/drivers/ethernet/ |
| D | phy_gecko.c | 83 ETH_TypeDef *const eth = phy->regs; in phy_read()
102 ETH_TypeDef *const eth = phy->regs; in phy_write()
143 ETH_TypeDef *const eth = phy->regs; in phy_gecko_init()
167 ETH_TypeDef *const eth = phy->regs; in phy_gecko_id_get()
193 ETH_TypeDef *const eth = phy->regs; in phy_gecko_auto_negotiate()
269 ETH_TypeDef *const eth = phy->regs; in phy_gecko_is_linked()
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| /Zephyr-latest/drivers/pwm/ |
| D | pwm_sam.c | 26 Pwm *regs; member
52 Pwm * const pwm = config->regs; in sam_pwm_set_cycles()
99 Pwm * const pwm = config->regs; in sam_pwm_init()
129 .regs = (Pwm *)DT_INST_REG_ADDR(inst), \
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| /Zephyr-latest/drivers/pcie/host/ |
| D | shell.c | 209 struct pcie_vc_regs regs; in show_vc() local
213 base = pcie_vc_cap_lookup(bdf, ®s); in show_vc()
222 regs.cap_reg_1.vc_count + 1, in show_vc()
223 regs.cap_reg_1.lpvc_count, in show_vc()
224 regs.cap_reg_1.pat_entry_size, in show_vc()
225 regs.cap_reg_2.vca_cap, in show_vc()
226 regs.cap_reg_2.vca_table_offset); in show_vc()
229 regs.cap_reg_1.vc_count + 1); in show_vc()
231 for (idx = 0; idx < regs.cap_reg_1.vc_count + 1; idx++) { in show_vc()
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| /Zephyr-latest/drivers/bbram/ |
| D | bbram_xec.c | 27 struct vbatr_regs *const regs = (struct vbatr_regs *)(DT_REG_ADDR_BY_NAME( in bbram_xec_check_invalid() local
30 if (regs->PFRS & BIT(MCHP_VBATR_PFRS_VBAT_RST_POS)) { in bbram_xec_check_invalid()
31 regs->PFRS |= BIT(MCHP_VBATR_PFRS_VBAT_RST_POS); in bbram_xec_check_invalid()
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| /Zephyr-latest/drivers/sensor/microchip/mchp_tach_xec/ |
| D | tach_mchp_xec.c | 30 struct tach_regs * const regs; member
56 struct tach_regs * const tach = cfg->regs; in tach_xec_sample_fetch()
133 struct tach_regs * const tach = cfg->regs; in tach_xec_pm_action()
161 struct tach_regs * const tach = cfg->regs; in tach_xec_init()
187 .regs = (struct tach_regs * const)DT_INST_REG_ADDR(inst), \
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| /Zephyr-latest/drivers/video/ |
| D | video_emul_imager.c | 56 const struct emul_imager_reg *regs[2]; member
104 {.fps = 15, .regs = {emul_imager_rgb565_64x20, emul_imager_rgb565_64x20_15fps}},
105 {.fps = 30, .regs = {emul_imager_rgb565_64x20, emul_imager_rgb565_64x20_30fps}},
106 {.fps = 60, .regs = {emul_imager_rgb565_64x20, emul_imager_rgb565_64x20_60fps}},
124 {.fps = 15, .regs = {emul_imager_yuyv_64x20, emul_imager_yuyv_64x20_15fps}},
125 {.fps = 30, .regs = {emul_imager_yuyv_64x20, emul_imager_yuyv_64x20_30fps}},
190 const struct emul_imager_reg *regs) in emul_imager_write_multi() argument
194 for (int i = 0; regs[i].addr != 0; i++) { in emul_imager_write_multi()
195 ret = emul_imager_write_reg(dev, regs[i].addr, regs[i].value); in emul_imager_write_multi()
250 ret = emul_imager_write_multi(dev, mode->regs[i]); in emul_imager_set_mode()
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| /Zephyr-latest/drivers/dma/ |
| D | dma_sam_xdmac.c | 40 Xdmac *regs; member
56 Xdmac * const xdmac = dev_cfg->regs; in sam_xdmac_isr()
87 Xdmac * const xdmac = dev_cfg->regs; in sam_xdmac_channel_configure()
130 Xdmac * const xdmac = dev_cfg->regs; in sam_xdmac_transfer_configure()
304 Xdmac * const xdmac = config->regs; in sam_xdmac_transfer_start()
329 Xdmac * const xdmac = config->regs; in sam_xdmac_transfer_stop()
356 Xdmac * const xdmac = dev_cfg->regs; in sam_xdmac_initialize()
383 Xdmac * const xdmac = dev_cfg->regs; in sam_xdmac_get_status()
419 .regs = (Xdmac *)DT_INST_REG_ADDR(0),
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| /Zephyr-latest/drivers/gpio/ |
| D | gpio_intel.c | 165 static inline mm_reg_t regs(const struct device *dev) in regs() function
197 val = sys_read32(regs(dev) + offset); in check_perm()
209 val = sys_read32(regs(dev) + offset); in check_perm()
238 reg = regs(dev) + REG_GPI_INT_STS_BASE_GET(data) + GPIO_INTERRUPT_BASE_GET(cfg); in gpio_intel_isr()
275 reg = regs(dev) + data->pad_base + (raw_pin * PIN_OFFSET); in gpio_intel_config()
351 reg = regs(dev) + REG_PAD_HOST_SW_OWNER_GET(data) + GPIO_BASE_GET(dev); in gpio_intel_pin_interrupt_configure()
356 reg = regs(dev) + data->pad_base + (raw_pin * PIN_OFFSET); in gpio_intel_pin_interrupt_configure()
361 reg_en = regs(dev) + REG_GPI_INT_EN_BASE_GET(data) + GPIO_BASE_GET(dev); in gpio_intel_pin_interrupt_configure()
367 reg_sts = regs(dev) + REG_GPI_INT_STS_BASE_GET(data) + GPIO_BASE_GET(dev); in gpio_intel_pin_interrupt_configure()
459 reg_addr = regs(dev) + data->pad_base + (raw_pin * PIN_OFFSET); in port_get_raw()
[all …]
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| /Zephyr-latest/arch/xtensa/core/ |
| D | gdbstub.c | 444 reg = &xtensa_gdb_ctx.regs[xtensa_gdb_ctx.a0_idx + idx]; in copy_to_ctx()
459 reg = &xtensa_gdb_ctx.regs[idx]; in copy_to_ctx()
476 wb_start = (uint8_t)xtensa_gdb_ctx.regs[xtensa_gdb_ctx.wb_idx].val; in copy_to_ctx()
495 xtensa_gdb_ctx.regs[ar_idx].val = xtensa_gdb_ctx.regs[a0_idx].val; in copy_to_ctx()
496 xtensa_gdb_ctx.regs[ar_idx].seqno = xtensa_gdb_ctx.regs[a0_idx].seqno; in copy_to_ctx()
544 reg = &xtensa_gdb_ctx.regs[xtensa_gdb_ctx.a0_idx + idx]; in restore_from_ctx()
555 reg = &xtensa_gdb_ctx.regs[idx]; in restore_from_ctx()
648 reg = &ctx->regs[idx]; in arch_gdb_reg_readall()
710 reg = &ctx->regs[idx]; in arch_gdb_reg_readone()
762 reg = &ctx->regs[idx]; in arch_gdb_reg_writeone()
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| D | gen_zsr.py | 53 regs = [ f"MISC{n}" for n in range(0, int(get("XCHAL_NUM_MISC_REGS"))) ] variable
66 regs.append(f"EXCSAVE{il}")
96 for i in range(len(NEEDED), len(regs)):
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| /Zephyr-latest/drivers/i2c/ |
| D | i2c_sam0.c | 34 SercomI2cm *regs; member
69 static void wait_synchronization(SercomI2cm *regs) in wait_synchronization() argument
73 while ((regs->SYNCBUSY.reg & SERCOM_I2CM_SYNCBUSY_MASK) != 0) { in wait_synchronization()
77 while ((regs->STATUS.reg & SERCOM_I2CM_STATUS_SYNCBUSY) != 0) { in wait_synchronization()
88 SercomI2cm *i2c = cfg->regs; in i2c_sam0_terminate_on_error()
138 SercomI2cm *i2c = cfg->regs; in i2c_sam0_isr()
229 SercomI2cm *i2c = cfg->regs; in i2c_sam0_dma_write_done()
266 SercomI2cm *i2c = cfg->regs; in i2c_sam0_dma_write_start()
320 SercomI2cm *i2c = cfg->regs; in i2c_sam0_dma_read_done()
358 SercomI2cm *i2c = cfg->regs; in i2c_sam0_dma_read_start()
[all …]
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| D | i2c_sam_twihs_rtio.c | 46 Twihs *regs; member
95 Twihs *const twihs = dev_cfg->regs; in i2c_sam_twihs_configure()
175 Twihs *const twihs = dev_cfg->regs; in i2c_sam_twihs_start()
205 Twihs *const twihs = dev_cfg->regs; in i2c_sam_twihs_complete()
231 Twihs *const twihs = dev_cfg->regs; in i2c_sam_twihs_isr()
292 Twihs *const twihs = dev_cfg->regs; in i2c_sam_twihs_initialize()
350 .regs = (Twihs *)DT_INST_REG_ADDR(n), \
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| D | i2c_sam_twihs.c | 45 Twihs *regs; member
107 Twihs *const twihs = dev_cfg->regs; in i2c_sam_twihs_configure()
186 Twihs *const twihs = dev_cfg->regs; in i2c_sam_twihs_transfer()
226 Twihs *const twihs = dev_cfg->regs; in i2c_sam_twihs_isr()
285 Twihs *const twihs = dev_cfg->regs; in i2c_sam_twihs_initialize()
339 .regs = (Twihs *)DT_INST_REG_ADDR(n), \
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| D | i2c_sam_twi.c | 45 Twi *regs; member
109 Twi *const twi = dev_cfg->regs; in i2c_sam_twi_configure()
192 Twi *const twi = dev_cfg->regs; in i2c_sam_twi_transfer()
254 Twi *const twi = dev_cfg->regs; in i2c_sam_twi_isr()
313 Twi *const twi = dev_cfg->regs; in i2c_sam_twi_initialize()
371 .regs = (Twi *)DT_INST_REG_ADDR(n), \
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| /Zephyr-latest/drivers/espi/ |
| D | espi_mchp_xec_host_v2.c | 158 struct espi_iom_regs *regs = (struct espi_iom_regs *)cfg->base_addr; in init_mbox0() local
160 regs->IOHBAR[IOB_MBOX] = ESPI_XEC_MBOX_BAR_ADDRESS | in init_mbox0()
397 struct espi_iom_regs *regs = (struct espi_iom_regs *)cfg->base_addr; in init_kbc0() local
404 regs->IOHBAR[IOB_KBC] = ESPI_XEC_KBC_BAR_ADDRESS | in init_kbc0()
550 struct espi_iom_regs *regs = (struct espi_iom_regs *)cfg->base_addr; in init_acpi_ec0() local
552 regs->IOHBAR[IOB_ACPI_EC0] = ESPI_XEC_ACPI_EC0_BAR_ADDRESS | in init_acpi_ec0()
642 struct espi_iom_regs *regs = (struct espi_iom_regs *)cfg->base_addr; in init_acpi_ec1() local
645 regs->IOHBAR[IOB_ACPI_EC1] = in init_acpi_ec1()
649 regs->IOHBAR[IOB_ACPI_EC1] = in init_acpi_ec1()
652 regs->IOHBAR[IOB_MBOX] = ESPI_XEC_MBOX_BAR_ADDRESS | in init_acpi_ec1()
[all …]
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| /Zephyr-latest/drivers/adc/ |
| D | adc_sam.c | 25 Adc *regs; member
70 Adc *const adc = cfg->regs; in adc_sam_channel_setup()
144 Adc *const adc = cfg->regs; in adc_sam_start_conversion()
157 Adc *const adc = cfg->regs; in adc_context_start_sampling()
262 Adc *const adc = cfg->regs; in adc_sam_isr()
285 Adc *const adc = cfg->regs; in adc_sam_init()
398 .regs = (Adc *)DT_INST_REG_ADDR(n), \
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| D | adc_sam0.c | 47 Adc *regs; member
119 Adc *const adc = cfg->regs; in adc_sam0_channel_setup()
268 Adc *const adc = cfg->regs; in adc_sam0_start_conversion()
322 Adc *const adc = cfg->regs; in start_read()
424 Adc *const adc = cfg->regs; in adc_sam0_isr()
449 Adc *const adc = cfg->regs; in adc_sam0_init()
529 Adc * const adc = cfg->regs; \
546 Adc * const adc = cfg->regs; \
566 .regs = (Adc *)DT_INST_REG_ADDR(n), \
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| /Zephyr-latest/drivers/dai/intel/ssp/ |
| D | ssp.c | 2080 const struct dai_intel_ipc4_ssp_config_ver_3_0 *regs = spec_config; in dai_ssp_set_reg_config() local
2082 uint32_t ssc0 = regs->ssc0; in dai_ssp_set_reg_config()
2083 sscr1 = regs->ssc1 & ~(SSCR1_RSVD21); in dai_ssp_set_reg_config()
2088 sys_write32(regs->ssc2 & ~SSCR2_SFRMEN, dai_base(dp) + SSCR2); /* hardware specific flow */ in dai_ssp_set_reg_config()
2090 sys_write32(regs->ssc2 | SSCR2_SFRMEN, dai_base(dp) + SSCR2); /* hardware specific flow */ in dai_ssp_set_reg_config()
2091 sys_write32(regs->ssc2, dai_base(dp) + SSCR2); in dai_ssp_set_reg_config()
2092 sys_write32(regs->sspsp, dai_base(dp) + SSPSP); in dai_ssp_set_reg_config()
2093 sys_write32(regs->sspsp2, dai_base(dp) + SSPSP2); in dai_ssp_set_reg_config()
2094 sys_write32(regs->ssioc, dai_base(dp) + SSIOC); in dai_ssp_set_reg_config()
2095 sys_write32(regs->sscto, dai_base(dp) + SSTO); in dai_ssp_set_reg_config()
[all …]
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| /Zephyr-latest/drivers/sensor/ti/bq274xx/ |
| D | bq274xx.c | 358 if (data->regs != &bq27427_regs) { in bq274xx_ensure_chemistry()
394 const struct bq274xx_regs *regs; in bq274xx_gauge_configure() local
401 if (data->regs == NULL) { in bq274xx_gauge_configure()
411 data->regs = &bq27421_regs; in bq274xx_gauge_configure()
413 data->regs = &bq27427_regs; in bq274xx_gauge_configure()
419 regs = data->regs; in bq274xx_gauge_configure()
453 regs->dm_design_capacity, config->design_capacity, in bq274xx_gauge_configure()
456 regs->dm_design_energy, designenergy_mwh, in bq274xx_gauge_configure()
459 regs->dm_terminate_voltage, config->terminate_voltage, in bq274xx_gauge_configure()
462 regs->dm_taper_rate, taperrate, in bq274xx_gauge_configure()
[all …]
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| /Zephyr-latest/drivers/memc/ |
| D | memc_sam_smc.c | 26 Smc *regs; member
53 bank = &cfg->regs->SMC_CS_NUMBER[cfg->banks[i].cs]; in memc_smc_init()
96 .regs = (Smc *)DT_INST_REG_ADDR(inst), \
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