Home
last modified time | relevance | path

Searched refs:reg_base (Results 26 – 50 of 50) sorted by relevance

12

/Zephyr-latest/lib/acpi/
Dacpi.c491 struct acpi_reg_base *reg_base = mmio_res->reg_base; in acpi_device_mmio_get() local
502 reg_base[mmio_cnt].type = ACPI_RES_TYPE_IO; in acpi_device_mmio_get()
503 reg_base[mmio_cnt].port = (uint32_t)res->Data.Io.Minimum; in acpi_device_mmio_get()
504 reg_base[mmio_cnt++].length = res->Data.Io.AddressLength; in acpi_device_mmio_get()
508 reg_base[mmio_cnt].type = ACPI_RES_TYPE_IO; in acpi_device_mmio_get()
509 reg_base[mmio_cnt].port = (uint32_t)res->Data.FixedIo.Address; in acpi_device_mmio_get()
510 reg_base[mmio_cnt++].length = res->Data.FixedIo.AddressLength; in acpi_device_mmio_get()
514 reg_base[mmio_cnt].type = ACPI_RES_TYPE_MEM; in acpi_device_mmio_get()
515 reg_base[mmio_cnt].mmio = (uintptr_t)res->Data.Memory24.Minimum; in acpi_device_mmio_get()
516 reg_base[mmio_cnt++].length = res->Data.Memory24.AddressLength; in acpi_device_mmio_get()
[all …]
Dacpi_shell.c283 struct acpi_reg_base reg_base[CONFIG_ACPI_MMIO_ENTRIES_MAX]; in get_acpi_dev_resource() local
298 mmio_res.mmio_max = ARRAY_SIZE(reg_base); in get_acpi_dev_resource()
299 mmio_res.reg_base = reg_base; in get_acpi_dev_resource()
/Zephyr-latest/drivers/gpio/
Dgpio_intel.c99 DEVICE_MMIO_NAMED_ROM(reg_base);
112 DEVICE_MMIO_NAMED_RAM(reg_base);
128 #define GPIO_REG_BASE_GET(dev) DEVICE_MMIO_NAMED_GET(dev, reg_base)
146 #define GPIO_REG_BASE_GET(dev) GPIO_REG_BASE(DEVICE_MMIO_NAMED_GET(dev, reg_base))
173 return GPIO_PAD_BASE(DEVICE_MMIO_NAMED_GET(dev, reg_base)); in pad_base()
578 device_map(&data->reg_base, res.reg_base, res.len, K_MEM_CACHE_NONE); in gpio_intel_acpi_enum()
643 device_map(&data->reg_base, in gpio_intel_dts_init()
644 cfg->reg_base.phys_addr & ~0xFFU, in gpio_intel_dts_init()
645 cfg->reg_base.size, in gpio_intel_dts_init()
648 DEVICE_MMIO_NAMED_MAP(dev, reg_base, K_MEM_CACHE_NONE); in gpio_intel_dts_init()
[all …]
Dgpio_rcar.c30 DEVICE_MMIO_NAMED_ROM(reg_base);
38 DEVICE_MMIO_NAMED_RAM(reg_base);
59 return sys_read32(DEVICE_MMIO_NAMED_GET(dev, reg_base) + offs); in gpio_rcar_read()
64 sys_write32(value, DEVICE_MMIO_NAMED_GET(dev, reg_base) + offs); in gpio_rcar_write()
265 DEVICE_MMIO_NAMED_MAP(dev, reg_base, K_MEM_CACHE_NONE); in gpio_rcar_init()
294 DEVICE_MMIO_NAMED_ROM_INIT(reg_base, DT_DRV_INST(n)), \
Dgpio_xlnx_ps.c52 DEVICE_MMIO_NAMED_MAP(dev, reg_base, K_MEM_CACHE_NONE); in gpio_xlnx_ps_init()
53 dev_data->base = DEVICE_MMIO_NAMED_GET(dev, reg_base); in gpio_xlnx_ps_init()
129 DEVICE_MMIO_NAMED_ROM_INIT(reg_base, DT_DRV_INST(idx)),\
Dgpio_ite_it8xxx2_v2.c385 volatile uint8_t *reg_base = in gpio_ite_isr() local
387 volatile uint8_t *reg_wuesr = reg_base + 1; in gpio_ite_isr()
456 volatile uint8_t *reg_base = (uint8_t *)gpio_config->wuc_base[pin]; local
457 volatile uint8_t *reg_wuemr = reg_base;
458 volatile uint8_t *reg_wuesr = reg_base + 1;
459 volatile uint8_t *reg_wubemr = reg_base + 3;
Dgpio_bcm2711.c52 DEVICE_MMIO_NAMED_ROM(reg_base);
63 DEVICE_MMIO_NAMED_RAM(reg_base);
314 DEVICE_MMIO_NAMED_MAP(port, reg_base, K_MEM_CACHE_NONE); in gpio_bcm2711_init()
315 data->base = DEVICE_MMIO_NAMED_GET(port, reg_base); in gpio_bcm2711_init()
345 DEVICE_MMIO_NAMED_ROM_INIT(reg_base, DT_INST_PARENT(n)), \
/Zephyr-latest/drivers/i2c/
Di2c_mcux_lpi2c.c44 DEVICE_MMIO_NAMED_ROM(reg_base);
61 DEVICE_MMIO_NAMED_RAM(reg_base);
81 LPI2C_Type *base = (LPI2C_Type *)DEVICE_MMIO_NAMED_GET(dev, reg_base); in mcux_lpi2c_configure()
157 LPI2C_Type *base = (LPI2C_Type *)DEVICE_MMIO_NAMED_GET(dev, reg_base); in mcux_lpi2c_transfer()
320 LPI2C_Type *base = (LPI2C_Type *)DEVICE_MMIO_NAMED_GET(dev, reg_base); in mcux_lpi2c_slave_irq_handler()
415 LPI2C_Type *base = (LPI2C_Type *)DEVICE_MMIO_NAMED_GET(dev, reg_base); in mcux_lpi2c_target_register()
463 LPI2C_Type *base = (LPI2C_Type *)DEVICE_MMIO_NAMED_GET(dev, reg_base); in mcux_lpi2c_target_unregister()
481 LPI2C_Type *base = (LPI2C_Type *)DEVICE_MMIO_NAMED_GET(dev, reg_base); in mcux_lpi2c_isr()
504 DEVICE_MMIO_NAMED_MAP(dev, reg_base, K_MEM_CACHE_NONE | K_MEM_DIRECT_MAP); in mcux_lpi2c_init()
506 base = (LPI2C_Type *)DEVICE_MMIO_NAMED_GET(dev, reg_base); in mcux_lpi2c_init()
[all …]
/Zephyr-latest/drivers/sdhc/
Dsdhc_cdns.c28 DEVICE_MMIO_NAMED_ROM(reg_base);
45 DEVICE_MMIO_NAMED_RAM(reg_base);
146 DEVICE_MMIO_NAMED_MAP(dev, reg_base, K_MEM_CACHE_NONE); in sdhc_cdns_init()
168 data->params.reg_base = DEVICE_MMIO_NAMED_GET(dev, reg_base); in sdhc_cdns_init()
272 reg_base, DT_DRV_INST(inst)), \
Dsdhc_cdns_ll.h469 uintptr_t reg_base; member
/Zephyr-latest/drivers/dma/
Ddma_pl330.c262 uint32_t reg_base, int ch, int secure) in dma_pl330_start_dma_ch() argument
271 data = sys_read32(reg_base + DMAC_PL330_DBGSTATUS); in dma_pl330_start_dma_ch()
281 reg_base + DMAC_PL330_DBGINST0); in dma_pl330_start_dma_ch()
284 reg_base + DMAC_PL330_DBGINST1); in dma_pl330_start_dma_ch()
286 sys_write32(0x0, reg_base + DMAC_PL330_DBGCMD); in dma_pl330_start_dma_ch()
290 data = sys_read32(reg_base + DMAC_PL330_DBGCMD); in dma_pl330_start_dma_ch()
300 static int dma_pl330_wait(uint32_t reg_base, int ch) in dma_pl330_wait() argument
303 uint32_t cs0_reg = reg_base + DMAC_PL330_CS0; in dma_pl330_wait()
358 ret = dma_pl330_start_dma_ch(dev, dev_cfg->reg_base, channel, in dma_pl330_xfer()
365 ret = dma_pl330_wait(dev_cfg->reg_base, channel); in dma_pl330_xfer()
[all …]
Ddma_pl330.h163 mem_addr_t reg_base; member
/Zephyr-latest/soc/intel/apollo_lake/
Dsoc_gpio.h293 #define GPIO_REG_BASE(reg_base) reg_base argument
295 #define GPIO_PAD_BASE(reg_base) \ argument
296 (sys_read32(reg_base + REG_PAD_BASE_ADDR))
/Zephyr-latest/drivers/pinctrl/renesas/rcar/
Dpfc_rcar.c33 static uintptr_t reg_base[] = { variable
319 if (reg_index >= ARRAY_SIZE(reg_base)) { in pinctrl_configure_pin()
323 pfc_base = reg_base[reg_index]; in pinctrl_configure_pin()
385 for (unsigned int i = 0; i < ARRAY_SIZE(reg_base); i++) { in pfc_rcar_driver_init()
386 device_map(reg_base + i, reg_base[i], reg_sizes[i], K_MEM_CACHE_NONE); in pfc_rcar_driver_init()
/Zephyr-latest/include/zephyr/drivers/gpio/
Dgpio_intel.h21 uintptr_t reg_base; member
/Zephyr-latest/soc/intel/common/
Dsoc_gpio.h8 uintptr_t reg_base; member
/Zephyr-latest/drivers/spi/
Dspi_mcux_lpspi.c64 DEVICE_MMIO_NAMED_ROM(reg_base);
76 DEVICE_MMIO_NAMED_RAM(reg_base);
98 LPSPI_Type *base = (LPSPI_Type *)DEVICE_MMIO_NAMED_GET(dev, reg_base); in spi_mcux_isr()
117 LPSPI_Type *base = (LPSPI_Type *)DEVICE_MMIO_NAMED_GET(dev, reg_base); in spi_mcux_transfer_next_packet()
149 LPSPI_Type *base = (LPSPI_Type *)DEVICE_MMIO_NAMED_GET(dev, reg_base); in spi_mcux_configure()
314 LPSPI_Type *base = (LPSPI_Type *)DEVICE_MMIO_NAMED_GET(dev, reg_base); in spi_mcux_dma_tx_load()
335 LPSPI_Type *base = (LPSPI_Type *)DEVICE_MMIO_NAMED_GET(dev, reg_base); in spi_mcux_dma_rx_load()
432 LPSPI_Type *base = (LPSPI_Type *)DEVICE_MMIO_NAMED_GET(dev, reg_base); in transceive_dma_sync()
489 LPSPI_Type *base = (LPSPI_Type *)DEVICE_MMIO_NAMED_GET(dev, reg_base); in transceive_dma()
551 LPSPI_Type *base = (LPSPI_Type *)DEVICE_MMIO_NAMED_GET(dev, reg_base); in spi_mcux_iodev_start()
[all …]
/Zephyr-latest/drivers/flash/
Dflash_cadence_qspi_nor.c128 cad_params->reg_base = DEVICE_MMIO_NAMED_GET(dev, qspi_reg); in flash_cad_init()
Dflash_cadence_qspi_nor_ll.h165 uintptr_t reg_base; member
/Zephyr-latest/drivers/dai/intel/dmic/
Ddmic.h174 uint32_t reg_base; member
Ddmic.c122 uint32_t dest = dmic->reg_base + reg; in dai_dmic_update_bits()
130 sys_write32(val, dmic->reg_base + reg); in dai_dmic_write()
136 return sys_read32(dmic->reg_base + reg); in dai_dmic_read()
912 .reg_base = DT_INST_REG_ADDR_BY_IDX(n, 0), \
Ddmic_nhlt.c29 sys_write32(val, dmic->reg_base + reg); in dai_dmic_write()
34 return sys_read32(dmic->reg_base + reg); in dai_dmic_read()
/Zephyr-latest/drivers/mspi/
Dmspi_ambiq_ap3.c48 uint32_t reg_base; member
924 if (sys_read32(cfg->reg_base) & MSPI_BUSY) { in mspi_ambiq_get_channel_status()
1423 .reg_base = DT_INST_REG_ADDR(n), \
/Zephyr-latest/dts/arm64/intel/
Dintel_socfpga_agilex5.dtsi129 reg-names = "reg_base", "combo_phy";
/Zephyr-latest/drivers/espi/
Despi_mchp_xec_host_v2.c84 uint32_t reg_base; /* logical device registers */ member

12