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/Zephyr-latest/subsys/shell/modules/kernel_service/thread/
DCMakeLists.txt12 zephyr_sources_ifdef(CONFIG_KERNEL_THREAD_SHELL_MASK mask.c)
/Zephyr-latest/drivers/firmware/scmi/
Dshmem.c159 void scmi_shmem_update_flags(const struct device *shmem, uint32_t mask, uint32_t val) in scmi_shmem_update_flags() argument
167 layout->chan_flags = (layout->chan_flags & ~mask) | (val & mask); in scmi_shmem_update_flags()
/Zephyr-latest/drivers/gpio/
Dgpio_efinix_sapphire.c140 static int gpio_efinix_sapphire_port_set_masked_raw(const struct device *dev, gpio_port_pins_t mask, in gpio_efinix_sapphire_port_set_masked_raw() argument
148 c_reg_val &= ~mask; in gpio_efinix_sapphire_port_set_masked_raw()
149 c_reg_val |= (value & mask); in gpio_efinix_sapphire_port_set_masked_raw()
Dgpio_neorv32.c98 gpio_port_pins_t mask, in neorv32_gpio_port_set_masked_raw() argument
105 data->output = (data->output & ~mask) | (mask & value); in neorv32_gpio_port_set_masked_raw()
Dgpio_npm6001.c166 gpio_port_pins_t mask, in gpio_npm6001_port_set_masked_raw() argument
171 ret = gpio_npm6001_port_set_bits_raw(dev, mask & value); in gpio_npm6001_port_set_masked_raw()
177 dev, mask & (~value & NPM6001_PIN_MSK)); in gpio_npm6001_port_set_masked_raw()
Dgpio_pca953x.c281 gpio_port_pins_t mask, in gpio_pca953x_port_write() argument
300 out = ((orig_out & ~mask) | (value & mask)) ^ toggle; in gpio_pca953x_port_write()
310 LOG_DBG("write %x msk %08x val %08x => %x: %d", orig_out, mask, in gpio_pca953x_port_write()
317 gpio_port_pins_t mask, in gpio_pca953x_port_set_masked() argument
320 return gpio_pca953x_port_write(dev, mask, value, 0); in gpio_pca953x_port_set_masked()
Dgpio_renesas_ra.c130 static int port_write(const struct device *dev, uint16_t value, uint16_t mask) in port_write() argument
132 const uint16_t set = value & mask; in port_write()
133 const uint16_t clr = (~value) & mask; in port_write()
302 static int gpio_ra_port_set_masked_raw(const struct device *dev, gpio_port_pins_t mask, in gpio_ra_port_set_masked_raw() argument
308 port_val = (port_val & ~mask) | (value & mask); in gpio_ra_port_set_masked_raw()
Dgpio_pca95xx.c541 uint32_t mask, uint32_t value) in gpio_pca95xx_port_set_masked_raw() argument
556 reg_out = (reg_out & ~mask) | (mask & value); in gpio_pca95xx_port_set_masked_raw()
566 uint32_t mask) in gpio_pca95xx_port_set_bits_raw() argument
568 return gpio_pca95xx_port_set_masked_raw(dev, mask, mask); in gpio_pca95xx_port_set_bits_raw()
572 uint32_t mask) in gpio_pca95xx_port_clear_bits_raw() argument
574 return gpio_pca95xx_port_set_masked_raw(dev, mask, 0); in gpio_pca95xx_port_clear_bits_raw()
578 uint32_t mask) in gpio_pca95xx_port_toggle_bits() argument
593 reg_out ^= mask; in gpio_pca95xx_port_toggle_bits()
/Zephyr-latest/lib/libc/minimal/source/string/
Dstring.c287 const uintptr_t mask = sizeof(mem_word_t) - 1; in memcpy() local
289 if ((((uintptr_t)d ^ (uintptr_t)s_byte) & mask) == 0) { in memcpy()
293 while (((uintptr_t)d_byte) & mask) { in memcpy()
/Zephyr-latest/drivers/interrupt_controller/
DKconfig.mtk_adsp8 bitfield registers (status and enable) and one mask value
Dintc_ioapic.c116 uint32_t mask);
533 uint32_t mask) argument
535 ioApicRedSetLo(irq, (ioApicRedGetLo(irq) & ~mask) | (value & mask));
/Zephyr-latest/subsys/testsuite/ztest/src/
Dztress.c174 uint32_t mask = active_mask; in preempt_update() local
176 while (mask) { in preempt_update()
177 int idx = 31 - __builtin_clz(mask); in preempt_update()
184 mask &= ~BIT(idx); in preempt_update()
209 uint32_t mask = BIT_MASK(31 - __builtin_clz((uint32_t)t.ticks)); in randomize_t() local
211 t.ticks += (sys_rand32_get() & mask); in randomize_t()
/Zephyr-latest/drivers/sensor/bosch/bmp388/
Dbmp388.c74 uint8_t mask, in bmp388_reg_field_update() argument
86 new_value = (old_value & ~mask) | (val & mask); in bmp388_reg_field_update()
145 uint32_t pos, mask; in bmp388_attr_set_oversampling() local
157 mask = BMP388_OSR_PRESSURE_MASK; in bmp388_attr_set_oversampling()
161 mask = BMP388_OSR_TEMP_MASK; in bmp388_attr_set_oversampling()
174 mask, in bmp388_attr_set_oversampling()
/Zephyr-latest/drivers/display/
Ddisplay_nrf_led_matrix.c227 static inline void move_to_next_pixel(uint8_t *mask, uint8_t *data, in move_to_next_pixel() argument
230 *mask <<= 1; in move_to_next_pixel()
231 if (!*mask) { in move_to_next_pixel()
232 *mask = 0x01; in move_to_next_pixel()
257 uint8_t mask = 0; in api_write() local
262 move_to_next_pixel(&mask, &data, &byte_buf); in api_write()
264 (data & mask) ? dev_data->brightness : 0; in api_write()
271 move_to_next_pixel(&mask, &data, &byte_buf); in api_write()
/Zephyr-latest/boards/m5stack/m5stack_atom_lite/
Dgrove_connectors.dtsi11 gpio-map-mask = <0xffffffff 0xffffffc0>;
/Zephyr-latest/boards/m5stack/m5stack_atoms3_lite/
Dgrove_connectors.dtsi11 gpio-map-mask = <0xffffffff 0xffffffc0>;
/Zephyr-latest/drivers/serial/
Duart_gecko.c254 uint32_t mask = USART_IEN_TXBL | USART_IEN_TXC; in uart_gecko_irq_tx_enable() local
256 USART_IntEnable(config->base, mask); in uart_gecko_irq_tx_enable()
262 uint32_t mask = USART_IEN_TXBL | USART_IEN_TXC; in uart_gecko_irq_tx_disable() local
264 USART_IntDisable(config->base, mask); in uart_gecko_irq_tx_disable()
288 uint32_t mask = USART_IEN_RXDATAV; in uart_gecko_irq_rx_enable() local
290 USART_IntEnable(config->base, mask); in uart_gecko_irq_rx_enable()
296 uint32_t mask = USART_IEN_RXDATAV; in uart_gecko_irq_rx_disable() local
298 USART_IntDisable(config->base, mask); in uart_gecko_irq_rx_disable()
312 uint32_t mask = USART_IEN_RXDATAV; in uart_gecko_irq_rx_ready() local
314 return (config->base->IEN & mask) in uart_gecko_irq_rx_ready()
/Zephyr-latest/dts/arm/nordic/
Dnrf54l_05_10_15_cpuapp.dtsi45 nordic,events-mask = <0x00100000>;
53 nordic,tasks-mask = <0x007f0000>;
/Zephyr-latest/include/zephyr/net/
Dsocketcan_utils.h96 zfilter->mask = sfilter->can_mask & BIT_MASK(29); in socketcan_to_can_filter()
113 sfilter->can_mask = zfilter->mask; in socketcan_from_can_filter()
/Zephyr-latest/include/zephyr/dt-bindings/clock/
Dstm32f7_clock.h66 #define STM32_DOMAIN_CLOCK(val, mask, shift, reg) \ argument
69 (((mask) & STM32_CLOCK_MASK_MASK) << STM32_CLOCK_MASK_SHIFT) | \
/Zephyr-latest/boards/m5stack/m5stack_core2/
Dgrove_connectors.dtsi11 gpio-map-mask = <0xffffffff 0xffffffc0>;
/Zephyr-latest/boards/atmel/sam/sam4s_xplained/
Dsam4s_xplained.dts71 gpio-map-mask = <0xffffffff 0xffffffc0>;
88 gpio-map-mask = <0xffffffff 0xffffffc0>;
105 gpio-map-mask = <0xffffffff 0xffffffc0>;
122 gpio-map-mask = <0xffffffff 0xffffffc0>;
/Zephyr-latest/include/zephyr/drivers/adc/
Dads114s0x.h29 gpio_port_pins_t mask,
/Zephyr-latest/drivers/sensor/nxp/fxos8700/
Dfxos8700.h149 uint8_t mask,
241 uint8_t mask,
260 uint8_t mask,
/Zephyr-latest/boards/st/stm32h735g_disco/
Dpmod_connector.dtsi11 gpio-map-mask = <0xffffffff 0xffffffc0>;

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