1 /*
2 * Copyright (c) 2017, Christian Taedcke
3 * Copyright (c) 2020 Lemonbeat GmbH
4 *
5 * SPDX-License-Identifier: Apache-2.0
6 */
7
8 #include <errno.h>
9 #include <zephyr/drivers/uart.h>
10 #include <zephyr/irq.h>
11 #include <zephyr/pm/device.h>
12 #include <em_usart.h>
13 #include <em_cmu.h>
14 #include <soc.h>
15
16 #ifdef CONFIG_PINCTRL
17 #include <zephyr/drivers/pinctrl.h>
18 #else
19 #include <em_gpio.h>
20 #endif /* CONFIG_PINCTRL */
21
22 #ifdef CONFIG_CLOCK_CONTROL
23 #include <zephyr/drivers/clock_control.h>
24 #include <zephyr/drivers/clock_control/clock_control_silabs.h>
25 #define GET_GECKO_USART_CLOCK(idx) \
26 .clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(idx)), \
27 .clock_cfg = SILABS_DT_INST_CLOCK_CFG(idx),
28 #elif DT_NODE_HAS_PROP(id, peripheral_id)
29 #define USART_PREFIX cmuClock_USART
30 #define UART_PREFIX cmuClock_UART
31 #define CLOCK_USART(id) _CONCAT(USART_PREFIX, id)
32 #define CLOCK_UART(id) _CONCAT(UART_PREFIX, id)
33 #define GET_GECKO_USART_CLOCK(id) \
34 .clock = CLOCK_USART(DT_INST_PROP(id, peripheral_id)),
35 #define GET_GECKO_UART_CLOCK(id) \
36 .clock = CLOCK_UART(DT_INST_PROP(id, peripheral_id)),
37 #else
38 #if (USART_COUNT == 1)
39 #define CLOCK_USART(ref) (((ref) == USART0) ? cmuClock_USART0 \
40 : -1)
41 #elif (USART_COUNT == 2)
42 #define CLOCK_USART(ref) (((ref) == USART0) ? cmuClock_USART0 \
43 : ((ref) == USART1) ? cmuClock_USART1 \
44 : -1)
45 #elif (USART_COUNT == 3)
46 #define CLOCK_USART(ref) (((ref) == USART0) ? cmuClock_USART0 \
47 : ((ref) == USART1) ? cmuClock_USART1 \
48 : ((ref) == USART2) ? cmuClock_USART2 \
49 : -1)
50 #elif (USART_COUNT == 4)
51 #define CLOCK_USART(ref) (((ref) == USART0) ? cmuClock_USART0 \
52 : ((ref) == USART1) ? cmuClock_USART1 \
53 : ((ref) == USART2) ? cmuClock_USART2 \
54 : ((ref) == USART3) ? cmuClock_USART3 \
55 : -1)
56 #elif (USART_COUNT == 5)
57 #define CLOCK_USART(ref) (((ref) == USART0) ? cmuClock_USART0 \
58 : ((ref) == USART1) ? cmuClock_USART1 \
59 : ((ref) == USART2) ? cmuClock_USART2 \
60 : ((ref) == USART3) ? cmuClock_USART3 \
61 : ((ref) == USART4) ? cmuClock_USART4 \
62 : -1)
63 #elif (USART_COUNT == 6)
64 #define CLOCK_USART(ref) (((ref) == USART0) ? cmuClock_USART0 \
65 : ((ref) == USART1) ? cmuClock_USART1 \
66 : ((ref) == USART2) ? cmuClock_USART2 \
67 : ((ref) == USART3) ? cmuClock_USART3 \
68 : ((ref) == USART4) ? cmuClock_USART4 \
69 : ((ref) == USART5) ? cmuClock_USART5 \
70 : -1)
71 #else
72 #error "Undefined number of USARTs."
73 #endif /* USART_COUNT */
74
75 #define CLOCK_UART(ref) (((ref) == UART0) ? cmuClock_UART0 \
76 : ((ref) == UART1) ? cmuClock_UART1 \
77 : -1)
78 #define GET_GECKO_USART_CLOCK(id) \
79 .clock = CLOCK_USART((USART_TypeDef *)DT_INST_REG_ADDR(id)),
80 #define GET_GECKO_UART_CLOCK(id) \
81 .clock = CLOCK_UART((USART_TypeDef *)DT_INST_REG_ADDR(id)),
82 #endif /* DT_NODE_HAS_PROP(id, peripheral_id) */
83
84 /* Helper define to determine if SOC supports hardware flow control */
85 #if ((_SILICON_LABS_32B_SERIES > 0) || \
86 (defined(_USART_ROUTEPEN_RTSPEN_MASK) && \
87 defined(_USART_ROUTEPEN_CTSPEN_MASK)))
88 #define HW_FLOWCONTROL_IS_SUPPORTED_BY_SOC
89 #endif
90
91 #define HAS_HFC_OR(inst) DT_INST_PROP(inst, hw_flow_control) ||
92
93 #define DT_DRV_COMPAT silabs_gecko_uart
94
95 /* Has any enabled uart instance hw-flow-control enabled? */
96 #define UART_GECKO_UART_HW_FLOW_CONTROL_ENABLED \
97 DT_INST_FOREACH_STATUS_OKAY(HAS_HFC_OR) 0
98
99 #undef DT_DRV_COMPAT
100 #define DT_DRV_COMPAT silabs_gecko_usart
101
102 /* Has any enabled usart instance hw-flow-control enabled? */
103 #define UART_GECKO_USART_HW_FLOW_CONTROL_ENABLED \
104 DT_INST_FOREACH_STATUS_OKAY(HAS_HFC_OR) 0
105
106 #if UART_GECKO_USART_HW_FLOW_CONTROL_ENABLED || \
107 UART_GECKO_UART_HW_FLOW_CONTROL_ENABLED
108 #define UART_GECKO_HW_FLOW_CONTROL
109 #endif
110
111 /* Sanity check for hardware flow control */
112 #if defined(UART_GECKO_HW_FLOW_CONTROL) && \
113 (!(defined(HW_FLOWCONTROL_IS_SUPPORTED_BY_SOC)))
114 #error "Hardware flow control is activated for at least one UART/USART, \
115 but not supported by this SOC"
116 #endif
117
118 #if defined(UART_GECKO_HW_FLOW_CONTROL) && \
119 (!defined(CONFIG_SOC_GECKO_HAS_INDIVIDUAL_PIN_LOCATION) && \
120 !defined(GPIO_USART_ROUTEEN_RTSPEN))
121 #error "Driver not supporting hardware flow control for this SOC"
122 #endif
123
124 /**
125 * @brief Config struct for UART
126 */
127
128 struct uart_gecko_config {
129 #ifdef CONFIG_PINCTRL
130 const struct pinctrl_dev_config *pcfg;
131 #endif /* CONFIG_PINCTRL */
132 USART_TypeDef *base;
133 #ifdef CONFIG_CLOCK_CONTROL
134 const struct device *clock_dev;
135 const struct silabs_clock_control_cmu_config clock_cfg;
136 #else
137 CMU_Clock_TypeDef clock;
138 #endif
139 uint32_t baud_rate;
140 #ifndef CONFIG_PINCTRL
141 #ifdef UART_GECKO_HW_FLOW_CONTROL
142 bool hw_flowcontrol;
143 #endif /* UART_GECKO_HW_FLOW_CONTROL */
144 #endif
145 #ifdef CONFIG_UART_INTERRUPT_DRIVEN
146 void (*irq_config_func)(const struct device *dev);
147 #endif /* CONFIG_UART_INTERRUPT_DRIVEN */
148 #ifndef CONFIG_PINCTRL
149 struct soc_gpio_pin pin_rx;
150 struct soc_gpio_pin pin_tx;
151 #ifdef UART_GECKO_HW_FLOW_CONTROL
152 struct soc_gpio_pin pin_rts;
153 struct soc_gpio_pin pin_cts;
154 #endif /* UART_GECKO_HW_FLOW_CONTROL */
155 #ifdef CONFIG_SOC_GECKO_HAS_INDIVIDUAL_PIN_LOCATION
156 uint8_t loc_rx;
157 uint8_t loc_tx;
158 #ifdef UART_GECKO_HW_FLOW_CONTROL
159 uint8_t loc_rts;
160 uint8_t loc_cts;
161 #endif /* UART_GECKO_HW_FLOW_CONTROL */
162 #else /* CONFIG_SOC_GECKO_HAS_INDIVIDUAL_PIN_LOCATION */
163 uint8_t loc;
164 #endif /* CONFIG_SOC_GECKO_HAS_INDIVIDUAL_PIN_LOCATION */
165 #endif
166 };
167
168 struct uart_gecko_data {
169 #ifdef CONFIG_UART_INTERRUPT_DRIVEN
170 uart_irq_callback_user_data_t callback;
171 void *cb_data;
172 #endif
173 };
174
uart_gecko_poll_in(const struct device * dev,unsigned char * c)175 static int uart_gecko_poll_in(const struct device *dev, unsigned char *c)
176 {
177 const struct uart_gecko_config *config = dev->config;
178 uint32_t flags = USART_StatusGet(config->base);
179
180 if (flags & USART_STATUS_RXDATAV) {
181 *c = USART_Rx(config->base);
182 return 0;
183 }
184
185 return -1;
186 }
187
uart_gecko_poll_out(const struct device * dev,unsigned char c)188 static void uart_gecko_poll_out(const struct device *dev, unsigned char c)
189 {
190 const struct uart_gecko_config *config = dev->config;
191
192 USART_Tx(config->base, c);
193 }
194
uart_gecko_err_check(const struct device * dev)195 static int uart_gecko_err_check(const struct device *dev)
196 {
197 const struct uart_gecko_config *config = dev->config;
198 uint32_t flags = USART_IntGet(config->base);
199 int err = 0;
200
201 if (flags & USART_IF_RXOF) {
202 err |= UART_ERROR_OVERRUN;
203 }
204
205 if (flags & USART_IF_PERR) {
206 err |= UART_ERROR_PARITY;
207 }
208
209 if (flags & USART_IF_FERR) {
210 err |= UART_ERROR_FRAMING;
211 }
212
213 USART_IntClear(config->base, USART_IF_RXOF |
214 USART_IF_PERR |
215 USART_IF_FERR);
216
217 return err;
218 }
219
220 #ifdef CONFIG_UART_INTERRUPT_DRIVEN
uart_gecko_fifo_fill(const struct device * dev,const uint8_t * tx_data,int len)221 static int uart_gecko_fifo_fill(const struct device *dev, const uint8_t *tx_data,
222 int len)
223 {
224 const struct uart_gecko_config *config = dev->config;
225 int num_tx = 0U;
226
227 while ((len - num_tx > 0) &&
228 (config->base->STATUS & USART_STATUS_TXBL)) {
229
230 config->base->TXDATA = (uint32_t)tx_data[num_tx++];
231 }
232
233 return num_tx;
234 }
235
uart_gecko_fifo_read(const struct device * dev,uint8_t * rx_data,const int len)236 static int uart_gecko_fifo_read(const struct device *dev, uint8_t *rx_data,
237 const int len)
238 {
239 const struct uart_gecko_config *config = dev->config;
240 int num_rx = 0U;
241
242 while ((len - num_rx > 0) &&
243 (config->base->STATUS & USART_STATUS_RXDATAV)) {
244
245 rx_data[num_rx++] = (uint8_t)config->base->RXDATA;
246 }
247
248 return num_rx;
249 }
250
uart_gecko_irq_tx_enable(const struct device * dev)251 static void uart_gecko_irq_tx_enable(const struct device *dev)
252 {
253 const struct uart_gecko_config *config = dev->config;
254 uint32_t mask = USART_IEN_TXBL | USART_IEN_TXC;
255
256 USART_IntEnable(config->base, mask);
257 }
258
uart_gecko_irq_tx_disable(const struct device * dev)259 static void uart_gecko_irq_tx_disable(const struct device *dev)
260 {
261 const struct uart_gecko_config *config = dev->config;
262 uint32_t mask = USART_IEN_TXBL | USART_IEN_TXC;
263
264 USART_IntDisable(config->base, mask);
265 }
266
uart_gecko_irq_tx_complete(const struct device * dev)267 static int uart_gecko_irq_tx_complete(const struct device *dev)
268 {
269 const struct uart_gecko_config *config = dev->config;
270 uint32_t flags = USART_IntGet(config->base);
271
272 USART_IntClear(config->base, USART_IF_TXC);
273
274 return (flags & USART_IF_TXC) != 0U;
275 }
276
uart_gecko_irq_tx_ready(const struct device * dev)277 static int uart_gecko_irq_tx_ready(const struct device *dev)
278 {
279 const struct uart_gecko_config *config = dev->config;
280 uint32_t flags = USART_IntGetEnabled(config->base);
281
282 return (flags & USART_IF_TXBL) != 0U;
283 }
284
uart_gecko_irq_rx_enable(const struct device * dev)285 static void uart_gecko_irq_rx_enable(const struct device *dev)
286 {
287 const struct uart_gecko_config *config = dev->config;
288 uint32_t mask = USART_IEN_RXDATAV;
289
290 USART_IntEnable(config->base, mask);
291 }
292
uart_gecko_irq_rx_disable(const struct device * dev)293 static void uart_gecko_irq_rx_disable(const struct device *dev)
294 {
295 const struct uart_gecko_config *config = dev->config;
296 uint32_t mask = USART_IEN_RXDATAV;
297
298 USART_IntDisable(config->base, mask);
299 }
300
uart_gecko_irq_rx_full(const struct device * dev)301 static int uart_gecko_irq_rx_full(const struct device *dev)
302 {
303 const struct uart_gecko_config *config = dev->config;
304 uint32_t flags = USART_IntGet(config->base);
305
306 return (flags & USART_IF_RXDATAV) != 0U;
307 }
308
uart_gecko_irq_rx_ready(const struct device * dev)309 static int uart_gecko_irq_rx_ready(const struct device *dev)
310 {
311 const struct uart_gecko_config *config = dev->config;
312 uint32_t mask = USART_IEN_RXDATAV;
313
314 return (config->base->IEN & mask)
315 && uart_gecko_irq_rx_full(dev);
316 }
317
uart_gecko_irq_err_enable(const struct device * dev)318 static void uart_gecko_irq_err_enable(const struct device *dev)
319 {
320 const struct uart_gecko_config *config = dev->config;
321
322 USART_IntEnable(config->base, USART_IF_RXOF |
323 USART_IF_PERR |
324 USART_IF_FERR);
325 }
326
uart_gecko_irq_err_disable(const struct device * dev)327 static void uart_gecko_irq_err_disable(const struct device *dev)
328 {
329 const struct uart_gecko_config *config = dev->config;
330
331 USART_IntDisable(config->base, USART_IF_RXOF |
332 USART_IF_PERR |
333 USART_IF_FERR);
334 }
335
uart_gecko_irq_is_pending(const struct device * dev)336 static int uart_gecko_irq_is_pending(const struct device *dev)
337 {
338 return uart_gecko_irq_tx_ready(dev) || uart_gecko_irq_rx_ready(dev);
339 }
340
uart_gecko_irq_update(const struct device * dev)341 static int uart_gecko_irq_update(const struct device *dev)
342 {
343 return 1;
344 }
345
uart_gecko_irq_callback_set(const struct device * dev,uart_irq_callback_user_data_t cb,void * cb_data)346 static void uart_gecko_irq_callback_set(const struct device *dev,
347 uart_irq_callback_user_data_t cb,
348 void *cb_data)
349 {
350 struct uart_gecko_data *data = dev->data;
351
352 data->callback = cb;
353 data->cb_data = cb_data;
354 }
355
uart_gecko_isr(const struct device * dev)356 static void uart_gecko_isr(const struct device *dev)
357 {
358 struct uart_gecko_data *data = dev->data;
359
360 if (data->callback) {
361 data->callback(dev, data->cb_data);
362 }
363 }
364 #endif /* CONFIG_UART_INTERRUPT_DRIVEN */
365
366 /**
367 * @brief Subroutine initializer of UART pins
368 *
369 * @param dev UART device to configure
370 */
371 #ifndef CONFIG_PINCTRL
uart_gecko_init_pins(const struct device * dev)372 static void uart_gecko_init_pins(const struct device *dev)
373 {
374 const struct uart_gecko_config *config = dev->config;
375
376 /* Configure RX and TX */
377 GPIO_PinModeSet(config->pin_rx.port, config->pin_rx.pin,
378 config->pin_rx.mode, config->pin_rx.out);
379 GPIO_PinModeSet(config->pin_tx.port, config->pin_tx.pin,
380 config->pin_tx.mode, config->pin_tx.out);
381
382 #ifdef CONFIG_SOC_GECKO_HAS_INDIVIDUAL_PIN_LOCATION
383 /* For SOCs with configurable pin locations (set in SOC Kconfig) */
384 config->base->ROUTEPEN = USART_ROUTEPEN_RXPEN | USART_ROUTEPEN_TXPEN;
385 config->base->ROUTELOC0 =
386 (config->loc_tx << _USART_ROUTELOC0_TXLOC_SHIFT) |
387 (config->loc_rx << _USART_ROUTELOC0_RXLOC_SHIFT);
388 config->base->ROUTELOC1 = _USART_ROUTELOC1_RESETVALUE;
389 #elif defined(USART_ROUTE_RXPEN) && defined(USART_ROUTE_TXPEN)
390 /* For olders SOCs with only one pin location */
391 config->base->ROUTE = USART_ROUTE_RXPEN | USART_ROUTE_TXPEN
392 | (config->loc << 8);
393 #elif defined(GPIO_USART_ROUTEEN_RXPEN) && defined(GPIO_USART_ROUTEEN_TXPEN)
394 GPIO->USARTROUTE[USART_NUM(config->base)].ROUTEEN =
395 GPIO_USART_ROUTEEN_TXPEN | GPIO_USART_ROUTEEN_RXPEN;
396 GPIO->USARTROUTE[USART_NUM(config->base)].TXROUTE =
397 (config->pin_tx.pin << _GPIO_USART_TXROUTE_PIN_SHIFT) |
398 (config->pin_tx.port << _GPIO_USART_TXROUTE_PORT_SHIFT);
399 GPIO->USARTROUTE[USART_NUM(config->base)].RXROUTE =
400 (config->pin_rx.pin << _GPIO_USART_RXROUTE_PIN_SHIFT) |
401 (config->pin_rx.port << _GPIO_USART_RXROUTE_PORT_SHIFT);
402 #endif /* CONFIG_SOC_GECKO_HAS_INDIVIDUAL_PIN_LOCATION */
403
404 #ifdef UART_GECKO_HW_FLOW_CONTROL
405 /* Configure HW flow control (RTS, CTS) */
406 if (config->hw_flowcontrol) {
407 GPIO_PinModeSet(config->pin_rts.port, config->pin_rts.pin,
408 config->pin_rts.mode, config->pin_rts.out);
409 GPIO_PinModeSet(config->pin_cts.port, config->pin_cts.pin,
410 config->pin_cts.mode, config->pin_cts.out);
411
412 #ifdef CONFIG_SOC_GECKO_HAS_INDIVIDUAL_PIN_LOCATION
413 config->base->ROUTEPEN =
414 USART_ROUTEPEN_RXPEN |
415 USART_ROUTEPEN_TXPEN |
416 USART_ROUTEPEN_RTSPEN |
417 USART_ROUTEPEN_CTSPEN;
418
419 config->base->ROUTELOC1 =
420 (config->loc_rts << _USART_ROUTELOC1_RTSLOC_SHIFT) |
421 (config->loc_cts << _USART_ROUTELOC1_CTSLOC_SHIFT);
422 #elif defined(GPIO_USART_ROUTEEN_RTSPEN) && defined(GPIO_USART_ROUTEEN_CTSPEN)
423 GPIO->USARTROUTE[USART_NUM(config->base)].ROUTEEN =
424 GPIO_USART_ROUTEEN_TXPEN |
425 GPIO_USART_ROUTEEN_RXPEN |
426 GPIO_USART_ROUTEPEN_RTSPEN |
427 GPIO_USART_ROUTEPEN_CTSPEN;
428
429 GPIO->USARTROUTE[USART_NUM(config->base)].RTSROUTE =
430 (config->pin_rts.pin << _GPIO_USART_RTSROUTE_PIN_SHIFT) |
431 (config->pin_rts.port << _GPIO_USART_RTSROUTE_PORT_SHIFT);
432 GPIO->USARTROUTE[USART_NUM(config->base)].CTSROUTE =
433 (config->pin_cts.pin << _GPIO_USART_CTSROUTE_PIN_SHIFT) |
434 (config->pin_cts.port << _GPIO_USART_CTSROUTE_PORT_SHIFT);
435 #endif /* CONFIG_SOC_GECKO_HAS_INDIVIDUAL_PIN_LOCATION */
436 }
437 #endif /* UART_GECKO_HW_FLOW_CONTROL */
438 }
439 #endif /* !CONFIG_PINCTRL */
440
441 /**
442 * @brief Main initializer for UART
443 *
444 * @param dev UART device to be initialized
445 * @return int 0
446 */
uart_gecko_init(const struct device * dev)447 static int uart_gecko_init(const struct device *dev)
448 {
449 #ifdef CONFIG_PINCTRL
450 int err;
451 #endif /* CONFIG_PINCTRL */
452 const struct uart_gecko_config *config = dev->config;
453
454 USART_InitAsync_TypeDef usartInit = USART_INITASYNC_DEFAULT;
455
456 /* The peripheral and gpio clock are already enabled from soc and gpio driver */
457 /* Enable USART clock */
458 #ifdef CONFIG_CLOCK_CONTROL
459 err = clock_control_on(config->clock_dev, (clock_control_subsys_t)&config->clock_cfg);
460 if (err < 0) {
461 return err;
462 }
463 #else
464 CMU_ClockEnable(config->clock, true);
465 #endif
466
467 /* Init USART */
468 usartInit.baudrate = config->baud_rate;
469 #ifdef UART_GECKO_HW_FLOW_CONTROL
470 usartInit.hwFlowControl = config->hw_flowcontrol ?
471 usartHwFlowControlCtsAndRts : usartHwFlowControlNone;
472 #endif
473 USART_InitAsync(config->base, &usartInit);
474
475 #ifdef CONFIG_PINCTRL
476 err = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT);
477 if (err < 0) {
478 return err;
479 }
480 #else
481 /* Initialize USART pins */
482 uart_gecko_init_pins(dev);
483 #endif /* CONFIG_PINCTRL */
484
485 #ifdef CONFIG_UART_INTERRUPT_DRIVEN
486 config->irq_config_func(dev);
487 #endif
488
489 return 0;
490 }
491
492 #ifdef CONFIG_PM_DEVICE
uart_gecko_pm_action(const struct device * dev,enum pm_device_action action)493 static int uart_gecko_pm_action(const struct device *dev, enum pm_device_action action)
494 {
495 __maybe_unused const struct uart_gecko_config *config = dev->config;
496
497 switch (action) {
498 case PM_DEVICE_ACTION_SUSPEND:
499 #ifdef USART_STATUS_TXIDLE
500 /* Wait for TX FIFO to flush before suspending */
501 while (!(USART_StatusGet(config->base) & USART_STATUS_TXIDLE)) {
502 }
503 #endif
504 break;
505
506 case PM_DEVICE_ACTION_RESUME:
507 break;
508
509 default:
510 return -ENOTSUP;
511 }
512
513 return 0;
514 }
515 #endif
516
517 static DEVICE_API(uart, uart_gecko_driver_api) = {
518 .poll_in = uart_gecko_poll_in,
519 .poll_out = uart_gecko_poll_out,
520 .err_check = uart_gecko_err_check,
521 #ifdef CONFIG_UART_INTERRUPT_DRIVEN
522 .fifo_fill = uart_gecko_fifo_fill,
523 .fifo_read = uart_gecko_fifo_read,
524 .irq_tx_enable = uart_gecko_irq_tx_enable,
525 .irq_tx_disable = uart_gecko_irq_tx_disable,
526 .irq_tx_complete = uart_gecko_irq_tx_complete,
527 .irq_tx_ready = uart_gecko_irq_tx_ready,
528 .irq_rx_enable = uart_gecko_irq_rx_enable,
529 .irq_rx_disable = uart_gecko_irq_rx_disable,
530 .irq_rx_ready = uart_gecko_irq_rx_ready,
531 .irq_err_enable = uart_gecko_irq_err_enable,
532 .irq_err_disable = uart_gecko_irq_err_disable,
533 .irq_is_pending = uart_gecko_irq_is_pending,
534 .irq_update = uart_gecko_irq_update,
535 .irq_callback_set = uart_gecko_irq_callback_set,
536 #endif
537 };
538
539 #undef DT_DRV_COMPAT
540 #define DT_DRV_COMPAT silabs_gecko_uart
541
542 #ifdef CONFIG_UART_INTERRUPT_DRIVEN
543 #define GECKO_UART_IRQ_HANDLER_DECL(idx) \
544 static void uart_gecko_config_func_##idx(const struct device *dev)
545 #define GECKO_UART_IRQ_HANDLER_FUNC(idx) \
546 .irq_config_func = uart_gecko_config_func_##idx,
547 #define GECKO_UART_IRQ_HANDLER(idx) \
548 static void uart_gecko_config_func_##idx(const struct device *dev) \
549 { \
550 IRQ_CONNECT(DT_INST_IRQ_BY_NAME(idx, rx, irq), \
551 DT_INST_IRQ_BY_NAME(idx, rx, priority), \
552 uart_gecko_isr, DEVICE_DT_INST_GET(idx), 0); \
553 IRQ_CONNECT(DT_INST_IRQ_BY_NAME(idx, tx, irq), \
554 DT_INST_IRQ_BY_NAME(idx, tx, priority), \
555 uart_gecko_isr, DEVICE_DT_INST_GET(idx), 0); \
556 \
557 irq_enable(DT_INST_IRQ_BY_NAME(idx, rx, irq)); \
558 irq_enable(DT_INST_IRQ_BY_NAME(idx, tx, irq)); \
559 }
560 #else /* CONFIG_UART_INTERRUPT_DRIVEN */
561 #define GECKO_UART_IRQ_HANDLER_DECL(idx)
562 #define GECKO_UART_IRQ_HANDLER_FUNC(idx)
563 #define GECKO_UART_IRQ_HANDLER(idx)
564 #endif /* CONFIG_UART_INTERRUPT_DRIVEN */
565
566 #ifdef CONFIG_SOC_GECKO_HAS_INDIVIDUAL_PIN_LOCATION
567 #define GECKO_UART_RX_TX_PIN_LOCATIONS(idx) \
568 .loc_rx = DT_INST_PROP_BY_IDX(idx, location_rx, 0), \
569 .loc_tx = DT_INST_PROP_BY_IDX(idx, location_tx, 0),
570 #define VALIDATE_GECKO_UART_RX_TX_PIN_LOCATIONS(idx)
571 #else
572 #define GECKO_UART_RX_TX_PIN_LOCATIONS(idx) \
573 .loc = DT_INST_PROP_BY_IDX(idx, location_rx, 0),
574 #define VALIDATE_GECKO_UART_RX_TX_PIN_LOCATIONS(idx) \
575 BUILD_ASSERT(DT_INST_PROP_BY_IDX(idx, location_rx, 0) == \
576 DT_INST_PROP_BY_IDX(idx, location_tx, 0), \
577 "DTS location-* properties must have identical value")
578 #endif
579
580 #define PIN_UART_RXD(idx) \
581 { \
582 DT_INST_PROP_BY_IDX(idx, location_rx, 1), \
583 DT_INST_PROP_BY_IDX(idx, location_rx, 2), \
584 gpioModeInput, 1 \
585 }
586 #define PIN_UART_TXD(idx) \
587 { \
588 DT_INST_PROP_BY_IDX(idx, location_tx, 1), \
589 DT_INST_PROP_BY_IDX(idx, location_tx, 2), \
590 gpioModePushPull, 1 \
591 }
592
593 #define GECKO_UART_RX_TX_PINS(idx) \
594 .pin_rx = PIN_UART_RXD(idx), \
595 .pin_tx = PIN_UART_TXD(idx),
596
597 #ifdef UART_GECKO_HW_FLOW_CONTROL
598
599 #ifdef CONFIG_SOC_GECKO_HAS_INDIVIDUAL_PIN_LOCATION
600 #define GECKO_UART_RTS_CTS_PIN_LOCATIONS(idx) \
601 .loc_rts = COND_CODE_1(DT_INST_PROP(idx, hw_flow_control), \
602 (DT_INST_PROP_BY_IDX(idx, location_rts, 0)), \
603 (0)), \
604 .loc_cts = COND_CODE_1(DT_INST_PROP(idx, hw_flow_control), \
605 (DT_INST_PROP_BY_IDX(idx, location_cts, 0)), \
606 (0)),
607 #define VALIDATE_GECKO_UART_RTS_CTS_PIN_LOCATIONS(idx) \
608 COND_CODE_1(DT_INST_PROP(idx, hw_flow_control), \
609 (BUILD_ASSERT(DT_INST_NODE_HAS_PROP(idx, location_rts) && \
610 DT_INST_NODE_HAS_PROP(idx, location_cts), \
611 "DTS location-rts and location-cts are mandatory")), \
612 ())
613 #else /* CONFIG_SOC_GECKO_HAS_INDIVIDUAL_PIN_LOCATION */
614 /* Hardware flow control not supported for these SOCs */
615 #define GECKO_UART_RTS_CTS_PIN_LOCATIONS(idx)
616 #define VALIDATE_GECKO_UART_RTS_CTS_PIN_LOCATIONS(idx)
617 #endif /* CONFIG_SOC_GECKO_HAS_INDIVIDUAL_PIN_LOCATION */
618
619 #define PIN_UART_RTS(idx) \
620 COND_CODE_1(DT_INST_PROP(idx, hw_flow_control), \
621 ({ \
622 DT_INST_PROP_BY_IDX(idx, location_rts, 1), \
623 DT_INST_PROP_BY_IDX(idx, location_rts, 2), \
624 gpioModePushPull, 1 \
625 }), \
626 ({0}))
627
628 #define PIN_UART_CTS(idx) \
629 COND_CODE_1(DT_INST_PROP(idx, hw_flow_control), \
630 ({ \
631 DT_INST_PROP_BY_IDX(idx, location_cts, 1), \
632 DT_INST_PROP_BY_IDX(idx, location_cts, 2), \
633 gpioModeInput, 1 \
634 }), \
635 ({0}))
636
637 #define GECKO_UART_RTS_CTS_PINS(idx) \
638 .pin_rts = PIN_UART_RTS(idx), \
639 .pin_cts = PIN_UART_CTS(idx),
640
641 #define GECKO_UART_HW_FLOW_CONTROL(idx) \
642 .hw_flowcontrol = DT_INST_PROP(idx, hw_flow_control),
643
644 #else /* UART_GECKO_HW_FLOW_CONTROL */
645
646 #define GECKO_UART_RTS_CTS_PIN_LOCATIONS(idx)
647 #define VALIDATE_GECKO_UART_RTS_CTS_PIN_LOCATIONS(idx)
648 #define GECKO_UART_RTS_CTS_PINS(idx)
649 #define GECKO_UART_HW_FLOW_CONTROL(idx)
650
651 #endif /* UART_GECKO_HW_FLOW_CONTROL */
652
653 #define GECKO_UART_INIT(idx) \
654 VALIDATE_GECKO_UART_RX_TX_PIN_LOCATIONS(idx); \
655 VALIDATE_GECKO_UART_RTS_CTS_PIN_LOCATIONS(idx); \
656 \
657 GECKO_UART_IRQ_HANDLER_DECL(idx); \
658 \
659 static const struct uart_gecko_config uart_gecko_cfg_##idx = { \
660 .base = (USART_TypeDef *)DT_INST_REG_ADDR(idx), \
661 GET_GECKO_UART_CLOCK(idx) \
662 .baud_rate = DT_INST_PROP(idx, current_speed), \
663 GECKO_UART_HW_FLOW_CONTROL(idx) \
664 GECKO_UART_RX_TX_PINS(idx) \
665 GECKO_UART_RTS_CTS_PINS(idx) \
666 GECKO_UART_RX_TX_PIN_LOCATIONS(idx) \
667 GECKO_UART_RTS_CTS_PIN_LOCATIONS(idx) \
668 GECKO_UART_IRQ_HANDLER_FUNC(idx) \
669 }; \
670 \
671 static struct uart_gecko_data uart_gecko_data_##idx; \
672 \
673 DEVICE_DT_INST_DEFINE(idx, uart_gecko_init, \
674 NULL, &uart_gecko_data_##idx, \
675 &uart_gecko_cfg_##idx, PRE_KERNEL_1, \
676 CONFIG_SERIAL_INIT_PRIORITY, \
677 &uart_gecko_driver_api); \
678 \
679 \
680 GECKO_UART_IRQ_HANDLER(idx)
681
682 DT_INST_FOREACH_STATUS_OKAY(GECKO_UART_INIT)
683
684 #undef DT_DRV_COMPAT
685 #define DT_DRV_COMPAT silabs_gecko_usart
686
687 #ifdef CONFIG_UART_INTERRUPT_DRIVEN
688 #define GECKO_USART_IRQ_HANDLER_DECL(idx) \
689 static void usart_gecko_config_func_##idx(const struct device *dev)
690 #define GECKO_USART_IRQ_HANDLER_FUNC(idx) \
691 .irq_config_func = usart_gecko_config_func_##idx,
692 #define GECKO_USART_IRQ_HANDLER(idx) \
693 static void usart_gecko_config_func_##idx(const struct device *dev) \
694 { \
695 IRQ_CONNECT(DT_INST_IRQ_BY_NAME(idx, rx, irq), \
696 DT_INST_IRQ_BY_NAME(idx, rx, priority), \
697 uart_gecko_isr, DEVICE_DT_INST_GET(idx), 0); \
698 IRQ_CONNECT(DT_INST_IRQ_BY_NAME(idx, tx, irq), \
699 DT_INST_IRQ_BY_NAME(idx, tx, priority), \
700 uart_gecko_isr, DEVICE_DT_INST_GET(idx), 0); \
701 \
702 irq_enable(DT_INST_IRQ_BY_NAME(idx, rx, irq)); \
703 irq_enable(DT_INST_IRQ_BY_NAME(idx, tx, irq)); \
704 }
705 #else
706 #define GECKO_USART_IRQ_HANDLER_DECL(idx)
707 #define GECKO_USART_IRQ_HANDLER_FUNC(idx)
708 #define GECKO_USART_IRQ_HANDLER(idx)
709 #endif
710
711 #ifdef CONFIG_PINCTRL
712 #define GECKO_USART_INIT(idx) \
713 PINCTRL_DT_INST_DEFINE(idx); \
714 GECKO_USART_IRQ_HANDLER_DECL(idx); \
715 PM_DEVICE_DT_INST_DEFINE(idx, uart_gecko_pm_action); \
716 \
717 static const struct uart_gecko_config usart_gecko_cfg_##idx = { \
718 .pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(idx), \
719 .base = (USART_TypeDef *)DT_INST_REG_ADDR(idx), \
720 GET_GECKO_USART_CLOCK(idx) \
721 .baud_rate = DT_INST_PROP(idx, current_speed), \
722 GECKO_USART_IRQ_HANDLER_FUNC(idx) \
723 }; \
724 \
725 static struct uart_gecko_data usart_gecko_data_##idx; \
726 \
727 DEVICE_DT_INST_DEFINE(idx, uart_gecko_init, PM_DEVICE_DT_INST_GET(idx),\
728 &usart_gecko_data_##idx, \
729 &usart_gecko_cfg_##idx, PRE_KERNEL_1, \
730 CONFIG_SERIAL_INIT_PRIORITY, \
731 &uart_gecko_driver_api); \
732 \
733 GECKO_USART_IRQ_HANDLER(idx)
734 #else
735 #define GECKO_USART_INIT(idx) \
736 VALIDATE_GECKO_UART_RX_TX_PIN_LOCATIONS(idx); \
737 VALIDATE_GECKO_UART_RTS_CTS_PIN_LOCATIONS(idx); \
738 \
739 GECKO_USART_IRQ_HANDLER_DECL(idx); \
740 PM_DEVICE_DT_INST_DEFINE(idx, uart_gecko_pm_action); \
741 \
742 static const struct uart_gecko_config usart_gecko_cfg_##idx = { \
743 .base = (USART_TypeDef *)DT_INST_REG_ADDR(idx), \
744 GET_GECKO_USART_CLOCK(idx) \
745 .baud_rate = DT_INST_PROP(idx, current_speed), \
746 GECKO_UART_HW_FLOW_CONTROL(idx) \
747 GECKO_UART_RX_TX_PINS(idx) \
748 GECKO_UART_RTS_CTS_PINS(idx) \
749 GECKO_UART_RX_TX_PIN_LOCATIONS(idx) \
750 GECKO_UART_RTS_CTS_PIN_LOCATIONS(idx) \
751 GECKO_USART_IRQ_HANDLER_FUNC(idx) \
752 }; \
753 \
754 static struct uart_gecko_data usart_gecko_data_##idx; \
755 \
756 DEVICE_DT_INST_DEFINE(idx, uart_gecko_init, PM_DEVICE_DT_INST_GET(idx),\
757 &usart_gecko_data_##idx, \
758 &usart_gecko_cfg_##idx, PRE_KERNEL_1, \
759 CONFIG_SERIAL_INIT_PRIORITY, \
760 &uart_gecko_driver_api); \
761 \
762 GECKO_USART_IRQ_HANDLER(idx)
763 #endif
764
765 DT_INST_FOREACH_STATUS_OKAY(GECKO_USART_INIT)
766
