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/Zephyr-latest/boards/st/nucleo_l432kc/doc/
Dindex.rst151 as well as main PLL clock. By default System clock is driven by PLL clock at 80MHz,
/Zephyr-latest/boards/st/nucleo_l433rc_p/doc/
Dindex.rst156 as well as main PLL clock. By default System clock is driven by PLL clock at 80MHz,
/Zephyr-latest/boards/st/stm32f429i_disc1/doc/
Dindex.rst137 as well as by the main PLL clock. By default the system clock is driven by the PLL clock at 168MHz,
/Zephyr-latest/boards/nordic/nrf9131ek/doc/
Dindex.rst43 the slow clock is 32.768 kHz. The frequency of the main clock
/Zephyr-latest/tests/bsim/bluetooth/host/misc/disconnect/tester/src/
Dmain.c623 int main(void) in main() function
/Zephyr-latest/dts/arm/renesas/ra/ra8/
Dr7fa8m1xh.dtsi15 xtal: clock-main-osc {
/Zephyr-latest/boards/arm/mps2/doc/
Dmps2_an385.rst231 The V2M MPS2 main clock is 24 MHz.
/Zephyr-latest/boards/ezurio/bl5340_dvk/doc/
Dindex.rst53 the slow clock is 32.768KHz. The frequency of the main clock
227 acts as the main controller, controlled via SPI.
/Zephyr-latest/subsys/testsuite/ztest/src/
Dztest.c1219 int main(void) in main() function
1458 int main(void) in main() function
/Zephyr-latest/share/sysbuild/cmake/modules/
Dsysbuild_extensions.cmake208 # MAIN indicates this application is the main application
282 CACHE INTERNAL "Kconfig fragment defined by main application"
290 CACHE INTERNAL "devicetree overlay file defined by main application"
/Zephyr-latest/soc/microchip/mec/
DKconfig268 and main 96 MHz clock (MCK):
/Zephyr-latest/drivers/net/
DKconfig256 This driver main advantage is that it is possible to use this driver without any
/Zephyr-latest/doc/kernel/memory_management/
Dvirtual_memory.rst80 | main kernel |
/Zephyr-latest/boards/seeed/lora_e5_mini/doc/
Dindex.rst130 main PLL clock. By default System clock is driven by the MSI clock at 48MHz.
/Zephyr-latest/boards/weact/mini_stm32h743/doc/
Dindex.rst128 as well as by the main PLL clock. By default, the System clock is driven
/Zephyr-latest/boards/weact/mini_stm32h7b0/doc/
Dindex.rst129 as well as by the main PLL clock. By default, the System clock is driven
/Zephyr-latest/boards/witte/linum/doc/
Dindex.rst344 oscillator, as well as the main PLL clock. By default, the System clock is
/Zephyr-latest/doc/services/retention/
Dindex.rst147 feature from the main application).
/Zephyr-latest/doc/services/device_mgmt/
Dmcumgr_backporting.rst17 …f the Zephyr code base <https://github.com/zephyrproject-rtos/zephyr/tree/main/subsys/mgmt/mcumgr>…
/Zephyr-latest/boards/st/stm32l476g_disco/doc/
Dindex.rst145 as well as the main PLL clock. By default the System clock is driven by the PLL clock at 80MHz,
/Zephyr-latest/samples/bluetooth/hci_uart_3wire/src/
Dmain.c769 int main(void) in main() function
/Zephyr-latest/tests/bsim/bluetooth/host/att/sequential/tester/src/
Dmain.c664 int main(void) in main() function
/Zephyr-latest/boards/st/nucleo_f746zg/doc/
Dindex.rst157 oscillator, as well as the main PLL clock. By default, the System clock is
/Zephyr-latest/boards/st/nucleo_f767zi/doc/
Dindex.rst163 oscillator, as well as the main PLL clock. By default, the System clock is
/Zephyr-latest/boards/st/nucleo_h743zi/doc/
Dindex.rst157 oscillator, as well as the main PLL clock. By default, the System clock is

1...<<717273747576777879