Searched refs:define (Results 26 – 50 of 408) sorted by relevance
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18 #define ROMABLE_REGION ICCM19 #define RAMABLE_REGION DCCM20 #define ROM_RAM_IN_SAME_REGION 023 #define ROMABLE_REGION FLASH24 #define RAMABLE_REGION SRAM25 #define ROM_RAM_IN_SAME_REGION 027 #define ROMABLE_REGION SRAM28 #define RAMABLE_REGION SRAM29 #define ROM_RAM_IN_SAME_REGION 135 #define MPU_MIN_SIZE 2048[all …]
39 #define WDT_TEST_FLAGS (... | WDT_DISABLE_SUPPORTED)49 #define WDT_TEST_FLAGS (... | WDT_FLAG_RESET_NONE_SUPPORTED |53 #define DEFAULT_FLAGS (WDT_FLAG_RESET_SOC)54 This define will be used in wdt_install_timeout() "correct" test step.57 #define MAX_INSTALLABLE_TIMEOUTS (8)61 #define WDT_TEST_FLAGS (... | WDT_FLAG_ONLY_ONE_TIMEOUT_VALUE_SUPPORTED)64 #define WDT_WINDOW_MAX_ALLOWED (0xFFFFFFFFU)72 #define WDT_TEST_FLAGS (... | WDT_OPT_PAUSE_IN_SLEEP_SUPPORTED |75 #define DEFAULT_OPTIONS (WDT_OPT_PAUSE_IN_SLEEP | WDT_OPT_PAUSE_HALTED_BY_DBG)76 This define will be used in wdt_setup() "correct" test step.[all …]
23 #define ROMABLE_REGION FLASH25 #define ROMABLE_REGION RAM27 #define RAMABLE_REGION RAM31 #define ROMSTART_ADDR CONFIG_ROMSTART_REGION_ADDRESS32 #define ROMSTART_SIZE (CONFIG_ROMSTART_REGION_SIZE * 1K)34 #define ROMSTART_REGION ROMABLE_REGION38 #define ROM_ADDR RAM_ADDR40 #define ROM_ADDR (CONFIG_FLASH_BASE_ADDRESS + CONFIG_FLASH_LOAD_OFFSET)44 #define ROM_END_OFFSET CONFIG_ROM_END_OFFSET46 #define ROM_END_OFFSET 0[all …]
17 #define PHYS_RAM_ADDR DT_REG_ADDR(DT_CHOSEN(zephyr_sram))18 #define PHYS_RAM_SIZE DT_REG_SIZE(DT_CHOSEN(zephyr_sram))21 #define FLASH_ROM_ADDR DT_REG_ADDR(DT_CHOSEN(zephyr_flash))22 #define FLASH_ROM_SIZE DT_REG_SIZE(DT_CHOSEN(zephyr_flash))30 #define KERNEL_BASE_ADDR \33 #define KERNEL_RAM_SIZE \36 #define PHYS_RAM_AVAIL \41 #define KERNEL_BASE_ADDR (PHYS_RAM_ADDR + CONFIG_SRAM_OFFSET)42 #define KERNEL_RAM_SIZE (PHYS_RAM_SIZE - CONFIG_SRAM_OFFSET)49 #define PHYS_LOAD_ADDR (PHYS_RAM_ADDR + CONFIG_SRAM_OFFSET)[all …]
8 #define DT_DRAM_BASE 1000009 #define DT_DRAM_SIZE DT_SIZE_K(256)
33 #define SRAM2_ADDR (DT_REG_ADDR(DT_NODELABEL(sram0)) + 32 * 1024)34 #define RAM_SIZE2 (CONFIG_HP_SRAM_RESERVE - 32 * 1024)36 #define SRAM3_ADDR (DT_REG_ADDR(DT_NODELABEL(sram3)))37 #define RAM_SIZE3 (DT_REG_SIZE(DT_NODELABEL(sram3)))39 #define SRAM4_ADDR ((DT_REG_ADDR(DT_NODELABEL(sram0)) - 512 * 1024 * 1024) + 16 * 1024)40 #define RAM_SIZE4 (16 * 1024)49 #define MPU_ALIGN(region_size) \
7 #define AON_C_OBJECT_FILE_IN_SECT(lsect, objfile) \11 #define AON_S_OBJECT_FILE_IN_SECT(lsect, objfile) \15 #define AON_IN_SECT(lsect) \
17 #define ROMABLE_REGION ROM19 #define ROMABLE_REGION RAM21 #define RAMABLE_REGION RAM23 #define _EXCEPTION_SECTION_NAME exceptions24 #define _RESET_SECTION_NAME reset29 #define ROM_BASE (DT_REG_ADDR(DT_CHOSEN(zephyr_flash)) + \32 #define ROM_BASE DT_REG_ADDR(DT_CHOSEN(zephyr_flash))34 #define ROM_SIZE DT_REG_SIZE(DT_CHOSEN(zephyr_flash))40 #define SPI_CTRL DT_PARENT(DT_CHOSEN(zephyr_flash))41 #define ROM_BASE DT_REG_ADDR_BY_IDX(SPI_CTRL, 1)[all …]
25 #define ROMABLE_REGION ROM26 #define RAMABLE_REGION RAM28 #define VECTOR_SIZE 0x10035 #define ROM_BASE (DT_REG_ADDR(DT_CHOSEN(zephyr_code_partition)))36 #define ROM_SIZE (DT_REG_SIZE(DT_CHOSEN(zephyr_code_partition)))38 #define VECTOR_BASE (ROM_BASE + CONFIG_ROM_START_OFFSET)42 #define ROM_BASE (DT_REG_ADDR(DT_CHOSEN(zephyr_code_partition)))43 #define ROM_SIZE (DT_REG_SIZE(DT_CHOSEN(zephyr_code_partition)) - VECTOR_BASE)45 #define VECTOR_BASE (ROM_BASE + ROM_SIZE)51 #define ROM_BASE DT_REG_ADDR(DT_CHOSEN(zephyr_flash))[all …]
7 #define TXQ23_SIZE 0x10808 #define SMU1_SIZE DT_REG_SIZE(DT_NODELABEL(smu1_data))9 #define SMU2_SIZE DT_REG_SIZE(DT_NODELABEL(smu2_data))
22 #define RAMABLE_REGION RAM :sram0_phdr23 #define ROMABLE_REGION RAM :sram0_phdr26 #define MMU_PAGE_ALIGN . = ALIGN(CONFIG_MMU_PAGE_SIZE);27 #define HDR_MMU_PAGE_ALIGN ALIGN(CONFIG_MMU_PAGE_SIZE)28 #define HDR_4K_OR_MMU_PAGE_ALIGN ALIGN(CONFIG_MMU_PAGE_SIZE)29 #define LAST_RAM_ALIGN MMU_PAGE_ALIGN31 #define MMU_PAGE_ALIGN . = ALIGN(4);32 #define HDR_MMU_PAGE_ALIGN ALIGN(4)33 #define HDR_4K_OR_MMU_PAGE_ALIGN ALIGN(4096)36 #define PHYS_SRAM0_ADDR (DT_REG_ADDR(DT_NODELABEL(sram0)))[all …]
9 #define ICCM_SIZE DT_SIZE_K(256)10 #define DCCM_SIZE DT_SIZE_K(256)
9 #define ICCM_SIZE DT_SIZE_K(512)10 #define DCCM_SIZE DT_SIZE_K(512)
9 #define ICCM_SIZE DT_SIZE_K(256)10 #define DCCM_SIZE DT_SIZE_K(128)
11 #define DDR_ADDR 8000000015 #define DDR_SIZE DT_SIZE_M(1)
15 #define _NORMAL_OUTER_INNER_WRITE_THROUGH_NON_SHAREABLE (1 << 17)16 #define _RO_Msk (7 << 24)
16 #define DT_FLASH_SIZE DT_SIZE_K(512)17 #define DT_FLASH_ADDR 84000000 /* DT_ADDR will add leading 0x where needed */24 #define DT_SRAM_SIZE DT_SIZE_K(128)25 #define DT_SRAM_ADDR 84080000 /* DT_ADDR will add leading 0x where needed */
39 #define RPO_SET(addr, reg) ((addr & 0x1fffffff) | (reg << 29))41 #define SEGSTART_CACHED RPO_SET(ALIGN(CONFIG_MMU_PAGE_SIZE), CONFIG_XTENSA_CACHED_REGION)42 #define SEGSTART_UNCACHED RPO_SET(ALIGN(CONFIG_MMU_PAGE_SIZE), CONFIG_XTENSA_UNCACHED_REGION)44 #define SEGSTART_CACHED RPO_SET(ALIGN(64), CONFIG_XTENSA_CACHED_REGION)45 #define SEGSTART_UNCACHED RPO_SET(ALIGN(64), CONFIG_XTENSA_UNCACHED_REGION)49 #define SEGSTART_CACHED ALIGN(CONFIG_MMU_PAGE_SIZE)50 #define SEGSTART_UNCACHED ALIGN(CONFIG_MMU_PAGE_SIZE)52 #define SEGSTART_CACHED .53 #define SEGSTART_UNCACHED .55 #define ucram ram[all …]
132 ; #define DT_N_<node path>_PINCTRL_NUM 2136 ; #define DT_N_<node path>_PINCTRL_IDX_0_EXISTS 1137 ; #define DT_N_<node path>_PINCTRL_IDX_1_EXISTS 1141 ; #define DT_N_<node path>_PINCTRL_NAME_default_EXISTS 1142 ; #define DT_N_<node path>_PINCTRL_NAME_sleep_EXISTS 1146 ; #define DT_N_<node path>_PINCTRL_NAME_default_IDX 0147 ; #define DT_N_<node path>_PINCTRL_NAME_sleep_IDX 1151 ; #define DT_N_<node path>_PINCTRL_NAME_default_IDX_0_PH <node id for 'bar'>188 ; #define DT_N_<node-1 path>_GPIO_HOGS_EXISTS 1189 ; #define DT_N_<node-2 path>_GPIO_HOGS_EXISTS 1[all …]
82 #define RV_E(op...) op83 #define RV_I(op...) /* unavailable */85 #define RV_E(op...) op86 #define RV_I(op...) op
10 #define sram_eth_node DT_NODELABEL(sram3)12 #define sram_eth_node DT_NODELABEL(sram2)
18 #define SRAM_START DT_REG_ADDR(DT_CHOSEN(zephyr_sram))19 #define SRAM_SIZE DT_REG_SIZE(DT_CHOSEN(zephyr_sram))
17 #define SRAM_START DT_REG_ADDR(DT_CHOSEN(zephyr_sram))18 #define SRAM_SIZE DT_REG_SIZE(DT_CHOSEN(zephyr_sram))
8 REGEX "^#define CONFIG_"12 …string(REGEX REPLACE "#define (CONFIG_[A-Za-z|_|0-9]*) (.*)" "GEN_ABSOLUTE_SYM_KCONFIG(\\1, \\2)" …
