Searched refs:default (Results 5201 – 5225 of 5614) sorted by relevance
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| /Zephyr-latest/boards/silabs/radio_boards/slwrb4180a/doc/ |
| D | index.rst | 91 The default configuration can be found in
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| /Zephyr-latest/boards/silabs/radio_boards/slwrb4255a/doc/ |
| D | index.rst | 60 The default configuration can be found in
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| /Zephyr-latest/boards/silabs/radio_boards/xg23_rb4210a/doc/ |
| D | index.rst | 94 The default configuration can be found in
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| /Zephyr-latest/boards/silabs/radio_boards/xg24_rb4187c/doc/ |
| D | index.rst | 92 The default configuration can be found in
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| /Zephyr-latest/boards/gd/gd32f450z_eval/doc/ |
| D | index.rst | 83 The GD32F450Z-EVAL board has one serial communication port. The default port
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| /Zephyr-latest/boards/gd/gd32f470i_eval/doc/ |
| D | index.rst | 87 The GD32F470I-EVAL board has one serial communication port. The default port
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| /Zephyr-latest/boards/mikroe/mini_m4_for_stm32/doc/ |
| D | mikroe_mini_m4_for_stm32.rst | 81 The default configuration can be found in
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| /Zephyr-latest/boards/rakwireless/rak11720/doc/ |
| D | index.rst | 64 The default configuration can be found in the defconfig file:
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| /Zephyr-latest/boards/actinius/icarus_bee/doc/ |
| D | index.rst | 92 memory maps. By default, all of the memory space (Flash, SRAM, and
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| /Zephyr-latest/boards/actinius/icarus_som/doc/ |
| D | index.rst | 92 memory maps. By default, all of the memory space (Flash, SRAM, and
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| /Zephyr-latest/boards/mikroe/clicker_2/doc/ |
| D | mikroe_clicker_2.rst | 47 The default configuration can be found in
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| /Zephyr-latest/dts/arm/nxp/ |
| D | nxp_rt1060.dtsi | 19 /* default fuse */
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| /Zephyr-latest/dts/arm/st/f3/ |
| D | stm32f373.dtsi | 40 * even for the default value
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| /Zephyr-latest/boards/atmel/sam0/samd20_xpro/doc/ |
| D | index.rst | 65 The default configuration can be found in the Kconfig
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| /Zephyr-latest/boards/renesas/rcar_h3ulcb/doc/ |
| D | rcar_h3ulcb_r7.rst | 113 …ed on Kingfisher daughter board) with settings 115200 8N1 without hardware flow control by default.
144 .. note:: Interfaces are set to 125 kbit/s by default.
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| /Zephyr-latest/boards/st/disco_l475_iot1/doc/ |
| D | index.rst | 132 The default configuration can be found in the defconfig file:
176 as well as main PLL clock. By default System clock is driven by PLL clock at 80MHz,
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| /Zephyr-latest/doc/services/binary_descriptors/ |
| D | index.rst | 51 in the endianness native to the SoC. ``west bindesc`` assumes little endian by default,
104 # Enable default build time binary descriptors
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| /Zephyr-latest/doc/services/input/ |
| D | gpio-kbd.rst | 19 detection (which is enabled by default).
166 The driver uses an 8-bit datatype to store the row state by default, which
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| /Zephyr-latest/boards/st/stm32l496g_disco/doc/ |
| D | index.rst | 149 The default configuration can be found in the defconfig file:
181 as well as the main PLL clock. By default the System clock is driven by the PLL clock at 80MHz,
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| /Zephyr-latest/boards/st/stm32u083c_dk/doc/ |
| D | index.rst | 172 The default configuration can be found in the defconfig file:
204 as well as main PLL clock. By default System clock is driven by PLL clock at
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| /Zephyr-latest/boards/st/stm32wb5mm_dk/doc/ |
| D | stm32wb5mm_dk.rst | 123 The default configuration can be found in the defconfig file:
161 as well as main PLL clock. By default System clock is driven by HSE clock at 32MHz.
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| /Zephyr-latest/doc/develop/west/ |
| D | basics.rst | 85 file is named :file:`west.yml` by default; this can be overridden using the
96 By default, the Zephyr :ref:`build system <build_overview>` uses west to get
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| /Zephyr-latest/boards/st/nucleo_h503rb/doc/ |
| D | index.rst | 145 The default configuration can be found in the defconfig and dts files:
171 as well as main PLL clock. By default System clock is driven by PLL clock at
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| /Zephyr-latest/boards/st/nucleo_l412rb_p/doc/ |
| D | index.rst | 156 The default configuration can be found in the defconfig file:
191 as well as main PLL clock. By default System clock is driven by PLL clock at 80MHz,
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| /Zephyr-latest/boards/st/nucleo_u031r8/doc/ |
| D | index.rst | 154 The default configuration can be found in the defconfig file:
181 as well as main PLL clock. By default System clock is driven by PLL clock at
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