Searched refs:core (Results 76 – 100 of 877) sorted by relevance
12345678910>>...36
| /Zephyr-latest/soc/raspberrypi/rpi_pico/rp2350/ |
| D | Kconfig.soc | 21 Use the RP2350A with a Cortex-M33 core in both 'sockets'.
31 Use the RP2350B with a Cortex-M33 core in both 'sockets'.
|
| /Zephyr-latest/boards/cdns/xt-sim/doc/ |
| D | index.rst | 7 synthesizable 32-bit RISC processor core. Processor and SOC vendors can select
92 Adding a user-defined Xtensa core
94 Add your own core to the list of supported cores as follows:
99 …$ $(which echo) -e "config ${XTENSA_CORE}\n\tbool \"${XTENSA_CORE} core\"\n" >> "soc/xtensa/Kconfi…
101 Create a folder for that core:
140 2. Select ``XTENSA core Selection``
141 a. Select appropriate core (example ``hifi3_bd5 core``)
160 The Xtensa executable can be run in the simulator either with a standalone core,
161 or with a core connected to simulated peripherals.
|
| /Zephyr-latest/soc/nordic/common/ |
| D | nrf54hx_nrf92x_mpu_regions.c | 10 #define USBHS_BASE DT_REG_ADDR_BY_NAME(DT_NODELABEL(usbhs), core)
11 #define USBHS_SIZE DT_REG_SIZE_BY_NAME(DT_NODELABEL(usbhs), core)
|
| /Zephyr-latest/boards/nxp/mimxrt1160_evk/ |
| D | board.cmake | 13 …ove V7.50 (Only support run cm4 image when debugging due to default boot core on board is cm7 core)
|
| /Zephyr-latest/tests/bsim/bluetooth/audio/ |
| D | Kconfig.sysbuild | 13 bool "HCI IPC image on network core"
21 # otherwise by default they would have gone to the net core.
|
| /Zephyr-latest/boards/snps/nsim/arc_classic/doc/ |
| D | index.rst | 10 * ARC processor core, which implements ARCv2 or ARCv3 ISA, please refer to
22 * ``nsim/nsim_em`` - ARC EM core v4.0 with two register banks, FastIRQ's, MPUv2, DSP options and
24 * ``nsim/nsim_em7d_v22`` - ARC EM core v3.0 with one register bank and FastIRQ's
25 * ``nsim/nsim_em11d`` - ARC EM core v4.0 with one register bank, no FastIRQ's, MPUv2, DSP options a…
27 * ``nsim/nsim_sem`` - ARC EM core v4.0 with secure features (thus "SEM", i.e. Secure EM) and MPUv4
28 * ``nsim/nsim_hs`` - ARCv2 HS core v2.1 with two register banks, FastIRQ's and MPUv3
29 * ``nsim/nsim_hs/smp`` - Dual-core ARCv2 HS core v2.1 with two register banks, FastIRQ's and MPUv3
30 * ``nsim/nsim_vpx5`` - ARCv2 VPX5 core, close to vpx5_integer_full template
31 * ``nsim/nsim_hs5x`` - 32-bit ARCv3 HS core with rich set of options
32 * ``nsim/nsim_hs6x`` - 64-bit ARCv3 HS core with rich set of options
[all …]
|
| /Zephyr-latest/boards/raytac/mdbt53_db_40/doc/ |
| D | index.rst | 12 dual-core SoC based on the Arm® Cortex®-M33 architecture, with:
14 * a full-featured Arm Cortex-M33F core with DSP instructions, FPU, and
16 the **application core**
17 * a secondary Arm Cortex-M33 core, with a reduced feature set, running
18 at a fixed 64 MHz, referred to as the **network core**.
21 core on the nRF5340 SoC. The ``raytac_mdbt53_db_40/nrf5340/cpuapp`` build target provides
22 support for the network core on the nRF5340 SoC.
52 - Dual-core Arm® Cortex® M33
109 - Implementation Defined Attribution Unit (`IDAU`_) on the application core.
119 nRF5340 application core supports the Armv8-M Security Extension.
[all …]
|
| /Zephyr-latest/boards/nxp/mimxrt1180_evk/ |
| D | board.cmake | 16 # Note: Only support run cm7 image when debugging due to default boot core on board is cm33 core
18 board_runner_args(linkserver "--core=cm7")
|
| /Zephyr-latest/boards/openisa/rv32m1_vega/support/ |
| D | openocd_rv32m1_vega_ri5cy.cfg | 25 # Select the TAP core we are using
28 # Select the debug unit core we are using. This debug unit as an option.
38 # Select core 0
46 flash bank $_CHIPNAME.flash0 rv32m1 0 0 0 0 $_TARGETNAME # For core 0
47 flash bank $_CHIPNAME.flash1 rv32m1 0x01000000 0 0 0 $_TARGETNAME # For core 1
|
| /Zephyr-latest/doc/kernel/object_cores/ |
| D | index.rst | 16 Each instance of an object embeds an object core field named ``obj_core``.
18 cores to form a singly linked list. Each object core also links to the their
45 core statistics. When enabled, the object type contains a pointer to a
48 core contains a pointer to the "raw" statistical information associated with
54 object core statistics as well as the structures used for both "raw" and
76 initialized for use with object cores and object core statistics.
119 Kernel objects that have already been integrated into the object core framework
122 framework need to both initialize the object core and link it. The following
123 code builds on the example above and initializes the object core.
175 integrated into the object core statistics framework can both retrieve queried
|
| /Zephyr-latest/soc/arm/fvp_aemv8r/ |
| D | Kconfig.soc | 25 core through pm_cpu_on(), it always succeeds because
26 it indeed bring up secondary core successfully.
|
| /Zephyr-latest/modules/hal_silabs/wiseconnect/ |
| D | CMakeLists.txt | 8 # components/device/silabs/si91x/mcu/core/chip/component/siwg917*.slcc
26 ${WISECONNECT_DIR}/components/device/silabs/si91x/mcu/core/config
27 ${WISECONNECT_DIR}/components/device/silabs/si91x/mcu/core/chip/inc
28 ${WISECONNECT_DIR}/components/device/silabs/si91x/mcu/core/chip/config
42 ${WISECONNECT_DIR}/components/device/silabs/si91x/mcu/core/chip/src/rsi_deepsleep_soc.c
43 ${WISECONNECT_DIR}/components/device/silabs/si91x/mcu/core/chip/src/system_si91x.c
55 …${WISECONNECT_DIR}/components/device/silabs/si91x/mcu/core/chip/src/iPMU_prog/iPMU_dotc/ipmu_apis.c
56 …${WISECONNECT_DIR}/components/device/silabs/si91x/mcu/core/chip/src/iPMU_prog/iPMU_dotc/rsi_system…
132 ${WISECONNECT_DIR}/components/device/silabs/si91x/mcu/core/chip/config
|
| /Zephyr-latest/samples/bluetooth/bap_unicast_client/ |
| D | README.rst | 43 You can build both the application core image and an appropriate controller image for the network
44 core with:
52 If you prefer to only build the application core image, you can do so by doing instead:
59 In that case you can pair this application core image with the
|
| /Zephyr-latest/samples/bluetooth/bap_unicast_server/ |
| D | README.rst | 43 You can build both the application core image and an appropriate controller image for the network
44 core with:
52 If you prefer to only build the application core image, you can do so by doing instead:
59 In that case you can pair this application core image with the
|
| /Zephyr-latest/samples/bluetooth/cap_acceptor/ |
| D | README.rst | 34 You can build both the application core image and an appropriate controller image for the network
35 core with:
43 If you prefer to only build the application core image, you can do so by doing instead:
50 In that case you can pair this application core image with the
|
| /Zephyr-latest/samples/bluetooth/cap_initiator/ |
| D | README.rst | 34 You can build both the application core image and an appropriate controller image for the network
35 core with:
43 If you prefer to only build the application core image, you can do so by doing instead:
50 In that case you can pair this application core image with the
|
| /Zephyr-latest/samples/bluetooth/pbp_public_broadcast_sink/ |
| D | README.rst | 36 You can build both the application core image and an appropriate controller image for the network
37 core with:
45 If you prefer to only build the application core image, you can do so by doing instead:
52 In that case you can pair this application core image with the
|
| /Zephyr-latest/samples/bluetooth/pbp_public_broadcast_source/ |
| D | README.rst | 36 You can build both the application core image and an appropriate controller image for the network
37 core with:
45 If you prefer to only build the application core image, you can do so by doing instead:
52 In that case you can pair this application core image with the
|
| /Zephyr-latest/tests/subsys/logging/log_blocking/ |
| D | REAME.md | 5 When the core log buffer becomes full, the logging subsystem can be configured to
12 becomes available again in the core log buffer.
59 backpressure (i.e. the core log buffer usage will tend to zero over time).
66 cause the core log buffer to approach 100% capacity. Since the output log rate
67 is still only matched with the input log rate, the core log buffer capacity
76 the core log buffer will approach 100% capacity and, eventually, stall the
83 driver code continue to submit logs, the core log buffer approaches 100%
84 capacity. Once the core log buffer is full, the log processing thread is
|
| /Zephyr-latest/scripts/pylib/twister/ |
| D | scl.py | 57 import pykwalify.core
64 c = pykwalify.core.Core(source_data=data, schema_data=schema)
|
| /Zephyr-latest/tests/bsim/bluetooth/ |
| D | tests.nrf5340bsim_nrf5340_cpunet.txt | 1 # Search paths(s) for tests which will be run in the nrf5340 net core (both app, host and controller
2 # built in the net core)
|
| /Zephyr-latest/cmake/emu/ |
| D | nsim.cmake | 18 list(APPEND MDB_OPTIONS && ${MDB} -pset=${PSET_NUM} -psetname=core${CORE_NUM})
23 set(MULTIFILES ${MULTIFILES}core${CORE_NUM},)
25 set(MULTIFILES ${MULTIFILES}core${CORE_NUM})
|
| /Zephyr-latest/boards/nxp/mimxrt1170_evk/doc/ |
| D | index.rst | 6 The dual core i.MX RT1170 runs on the Cortex-M7 core at 1 GHz and on the Cortex-M4
262 | Cortex M7 | 0x30000000[630K] | primary core |
288 running at 996MHz. When targeting the M4 core, SysTick will also be used,
323 Dual core samples load the M4 core image from flash into the shared ``ocram``
324 region. The M7 core then sets the M4 boot address to this region. The only
325 sample currently enabled for dual core builds is the ``openamp`` sample.
326 To flash a dual core sample, the M4 image must be flashed first, so that it is
330 The secondary core can be debugged normally in single core builds
331 (where the target is ``mimxrt1170_evk/mimxrt1176/cm4``). For dual core builds, the
332 secondary core should be placed into a loop, then a debugger can be attached
[all …]
|
| /Zephyr-latest/tests/boards/altera_max10/i2c_master/ |
| D | README.txt | 2 Altera Nios-II I2C master soft IP core.
|
| /Zephyr-latest/tests/boards/altera_max10/qspi/ |
| D | README.txt | 2 Altera Nios-II QSPI flash soft IP core.
|
12345678910>>...36
