| /Zephyr-latest/samples/bluetooth/direction_finding_central/boards/ |
| D | nrf5340dk_nrf5340_cpuapp.overlay | 7 /* Enable pin forwarding to network core. The selected pins will be used by
11 * network core DTS overlay.
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| /Zephyr-latest/samples/bluetooth/direction_finding_connectionless_rx/boards/ |
| D | nrf5340dk_nrf5340_cpuapp.overlay | 7 /* Enable pin forwarding to network core. The selected pins will be used by
11 * network core DTS overlay.
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| /Zephyr-latest/samples/bluetooth/direction_finding_connectionless_tx/boards/ |
| D | nrf5340dk_nrf5340_cpuapp.overlay | 7 /* Enable pin forwarding to network core. The selected pins will be used by
11 * network core DTS overlay.
|
| /Zephyr-latest/samples/bluetooth/direction_finding_peripheral/boards/ |
| D | nrf5340dk_nrf5340_cpuapp.overlay | 7 /* Enable pin forwarding to network core. The selected pins will be used by
11 * network core DTS overlay.
|
| /Zephyr-latest/boards/ezurio/bl5340_dvk/doc/ |
| D | index.rst | 6 BL5340 module which is powered by a dual-core Nordic Semiconductor
8 dual-core SoC based on the Arm® Cortex®-M33 architecture, with:
10 * a full-featured Arm Cortex-M33F core with DSP instructions, FPU, and
12 the **application core**
13 * a secondary Arm Cortex-M33 core, with a reduced feature set, running
14 at a fixed 64 MHz, referred to as the **network core**.
17 core on the BL5340 module. The ``bl5340_dvk/nrf5340/cpunet`` build target provides
18 support for the network core on the BL5340 module. If ARM TrustZone is
20 non-secure partition of the application core on the BL5340 module.
185 core. The IDAU is implemented with the System Protection Unit and is
[all …]
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| /Zephyr-latest/boards/st/stm32h745i_disco/ |
| D | stm32h745i_disco_stm32h745xx_m7_defconfig | 14 # Enable UART ( disable to assign to M4 core)
17 # Console ( disable to assign to M4 core)
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| /Zephyr-latest/boards/nxp/mimxrt700_evk/ |
| D | board.cmake | 11 board_runner_args(linkserver "--core=cm33_core0")
15 board_runner_args(linkserver "--core=cm33_core1")
|
| /Zephyr-latest/soc/nxp/lpc/lpc55xxx/ |
| D | Kconfig | 97 core clock value at it's highest frequency which clocks at 150MHz.
99 this PLL should not be used as the core clock in those cases.
102 bool "LPC55xxx's second core"
106 hex "Address the second core will boot at"
109 This is the address the second core will boot from.
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| D | Kconfig.defconfig | 14 # Indicates the second core will be enabled, and the part will run
15 # in dual core mode.
22 # Move the LMA for the second core image to be in the flash region of primary
23 # core, so that JLink flash will load it correctly.
|
| /Zephyr-latest/boards/nxp/s32z2xxdc2/ |
| D | board.cmake | 17 board_runner_args(nxp_s32dbg "--core-name" "R52_${CONFIG_NXP_S32_RTU_INDEX}_0_LS")
20 board_runner_args(nxp_s32dbg "--core-name" "R52_${CONFIG_NXP_S32_RTU_INDEX}_0")
|
| /Zephyr-latest/boards/nordic/nrf54h20dk/doc/ |
| D | index.rst | 19 * an Arm Cortex-M33 core with DSP instructions, FPU, and Armv8-M Security
20 Extensions, running at up to 320 MHz, referred to as the **application core**
21 * an Arm Cortex-M33 core with DSP instructions, FPU, and Armv8-M Security
22 Extensions, running at up to 256 MHz, referred to as the **radio core**.
23 * a Nordic VPR RISC-V core, referred to as the **ppr core** (Peripheral
27 the application core on the nRF54H20 SoC.
29 the radio core on the nRF54H20 SoC.
31 the PPR core on the nRF54H20 SoC executing from RAM.
33 the PPR core on the nRF54H20 SoC executing from MRAM.
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| /Zephyr-latest/samples/philosophers/ |
| D | README.rst | 89 arch_cpu_idle () at zephyr/mainline/zephyr/arch/arm/core/cpu_idle.S:107
93 …, prio:40,useropts:1) arch_cpu_idle () at zephyr/mainline/zephyr/arch/arm/core/cpu_idle.S:107
124 arch_cpu_idle () at zephyr/mainline/zephyr/arch/arm/core/cpu_idle.S:107
128 …0 UNKNOWN PRIO 40) arch_cpu_idle () at zephyr/mainline/zephyr/arch/arm/core/cpu_idle.S:107
129 …ilosopher 0 PENDING PRIO 3) arch_swap (key=0) at zephyr/mainline/zephyr/arch/arm/core/swap.c:53
130 …1 SUSPENDED PRIO 2) arch_swap (key=key@entry=0) at zephyr/mainline/zephyr/arch/arm/core/swap.c:53
131 …2 SUSPENDED PRIO 1) arch_swap (key=key@entry=0) at zephyr/mainline/zephyr/arch/arm/core/swap.c:53
132 …3 SUSPENDED PRIO 0) arch_swap (key=key@entry=0) at zephyr/mainline/zephyr/arch/arm/core/swap.c:53
133 …ilosopher 4 PENDING PRIO 255) arch_swap (key=0) at zephyr/mainline/zephyr/arch/arm/core/swap.c:53
134 …5 SUSPENDED PRIO 254) arch_swap (key=key@entry=0) at zephyr/mainline/zephyr/arch/arm/core/swap.c:53
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| /Zephyr-latest/scripts/west_commands/runners/ |
| D | linkserver.py | 16 from runners.core import RunnerCaps, ZephyrBinaryRunner
24 def __init__(self, cfg, device, core, argument
41 self.core = core
99 return LinkServerBinaryRunner(cfg, args.device, args.core,
127 if self.core is not None:
128 _cmd_core = [ "-c", self.core ]
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| /Zephyr-latest/arch/xtensa/core/ |
| D | CMakeLists.txt | 45 # -dM, supported by all Xtensa toolchains) core-isa.h file available
46 # as "core-isa-dM.h". This can be easily parsed by non-C tooling.
49 # are the official places where we find core-isa.h. (Also that we
52 set(CORE_ISA_DM ${CMAKE_BINARY_DIR}/zephyr/include/generated/zephyr/core-isa-dM.h)
53 set(CORE_ISA_IN ${CMAKE_BINARY_DIR}/zephyr/include/generated/core-isa-dM.c)
54 file(WRITE ${CORE_ISA_IN} "#include <xtensa/config/core-isa.h>\n")
65 # THREADPTR is in core-isa.h which can be parsed in gen_zsr.py.
|
| /Zephyr-latest/doc/services/logging/ |
| D | cs_stm.rst | 11 access the STM without being aware of each other. Each core has 65536 stimulus ports (identical
18 Local domain (each core) has access to its own set of STMESP peripherals. Each set has registers fo…
27 When ETR is used then one core in the system is responsible for processing that data, for example
59 content is written to STMESP. Early logging is applicable only to the core which owns and configures
60 Coresight infrastructure (e.g. in case of NRF54H20 it is the Secure core).
91 Each core (local domain) is using logging frontend which writes logging data to STMESP registers.
96 If ETR RAM buffer is used then buffer owner core (``proxy``) is responsible for handling that data.
110 If the data goes to the ETR buffer, the proxy core's responsibility is to dump this data.
117 * It reduces the amount of data that needs to be sent to and processed by the application core, as …
120 Proxy core is using Nordic specific peripheral (TBM) to get ETR buffer busyness and send data over
[all …]
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| /Zephyr-latest/boards/nxp/s32z2xxdc2/support/ |
| D | startup.cmm | 15 ; - core core index, relative to the RTU *
18 ; - lockstep set to "yes" to start the core in lock-step mode *
32 &core=STRing.SCANAndExtract("&args","core=","0")
51 IF (&core<0||&core>3)
53 PRINT %ERROR "Invalid core number: &core"
77 &coreId=&core+1
126 ; Wake up core
127 GOSUB EnableR52_&(rtu)_&(core)
242 ; EnableR52_<core>_<rtu> - routines for waking up the RTU cores:
244 ; - enable core clock
[all …]
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| /Zephyr-latest/boards/nxp/mimxrt1160_evk/doc/ |
| D | index.rst | 6 The dual core i.MX RT1160 runs on the Cortex-M7 core at 600 MHz and on the
199 | Cortex M7 | 0x30000000[630K] | primary core |
225 running at 600MHz. When targeting the M4 core, SysTick will also be used,
247 Dual core samples load the M4 core image from flash into the shared ``ocram``
248 region. The M7 core then sets the M4 boot address to this region. The only
249 sample currently enabled for dual core builds is the ``openamp`` sample.
250 To flash a dual core sample, the M4 image must be flashed first, so that it is
254 The secondary core can be debugged normally in single core builds
255 (where the target is ``mimxrt1160_evk/mimxrt1166/cm4``). For dual core builds, the
256 secondary core should be placed into a loop, then a debugger can be attached
[all …]
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| /Zephyr-latest/cmake/toolchain/xcc/ |
| D | common.cmake | 24 set(XTENSA_CORE_LOCAL_C_FLAG "--xtensa-core=${XTENSA_CORE_${NORMALIZED_BOARD_TARGET}}")
25 list(APPEND TOOLCHAIN_C_FLAGS "--xtensa-core=${XTENSA_CORE_${NORMALIZED_BOARD_TARGET}}")
28 # the toolchain can have a default core configuration to use.
|
| /Zephyr-latest/boards/nxp/vmu_rt1170/ |
| D | board.cmake | 12 …ove V7.50 (Only support run cm4 image when debugging due to default boot core on board is cm7 core)
|
| /Zephyr-latest/arch/arc/core/ |
| D | arc_connect.c | 21 void z_arc_connect_ici_generate(uint32_t core) in z_arc_connect_ici_generate() argument
24 z_arc_connect_cmd(ARC_CONNECT_CMD_INTRPT_GENERATE_IRQ, core); in z_arc_connect_ici_generate()
29 void z_arc_connect_ici_ack(uint32_t core) in z_arc_connect_ici_ack() argument
32 z_arc_connect_cmd(ARC_CONNECT_CMD_INTRPT_GENERATE_ACK, core); in z_arc_connect_ici_ack()
37 uint32_t z_arc_connect_ici_read_status(uint32_t core) in z_arc_connect_ici_read_status() argument
42 z_arc_connect_cmd(ARC_CONNECT_CMD_INTRPT_READ_STATUS, core); in z_arc_connect_ici_read_status()
|
| /Zephyr-latest/boards/beagle/beagley_ai/doc/ |
| D | index.rst | 16 BeagleY-AI defaults to single-core mode for the R5 subsystem. Changes in that
35 module supports 512 interrupt inputs per R5F core. Each interrupt can be either
36 a level or a pulse (both active-high). The VIM has two interrupt outputs per core
60 The AM67A does not have a separate flash for the R5 core. Because of this
61 an A53 core has to load the program for the R5 core to the right memory
63 This can be done from Linux on the A53 core via remoteproc.
66 the R5 core always sees its local TCMA at address 0x00000000 and its TCMB0
|
| /Zephyr-latest/boards/raytac/mdbt53v_db_40/doc/ |
| D | index.rst | 12 dual-core SoC based on the Arm® Cortex®-M33 architecture, with:
14 * a full-featured Arm Cortex-M33F core with DSP instructions, FPU, and
16 the **application core**
17 * a secondary Arm Cortex-M33 core, with a reduced feature set, running
18 at a fixed 64 MHz, referred to as the **network core**.
21 core on the nRF5340 SoC. The raytac_mdbt53v_db_40_nrf5340_cpuapp build target provides
22 support for the network core on the nRF5340 SoC.
51 - Dual-core Arm® Cortex® M33
113 - Implementation Defined Attribution Unit (`IDAU`_) on the application core.
123 nRF5340 application core supports the Armv8-M Security Extension.
[all …]
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| /Zephyr-latest/boards/m5stack/m5stack_core2/doc/ |
| D | index.rst | 10 - ESP32-D0WDQ6-V3 chip (240MHz dual core, 600 DMIPS, 520KB SRAM, Wi-Fi)
33 .. _MPU-ESP32: https://m5stack.oss-cn-shenzhen.aliyuncs.com/resource/docs/datasheet/core/esp32_data…
34 .. _TOUCH-FT6336U: https://m5stack.oss-cn-shenzhen.aliyuncs.com/resource/docs/datasheet/core/Ft6336…
35 .. _SND-NS4168: https://m5stack.oss-cn-shenzhen.aliyuncs.com/resource/docs/datasheet/core/NS4168_CN…
36 .. _MPU-6886: https://m5stack.oss-cn-shenzhen.aliyuncs.com/resource/docs/datasheet/core/MPU-6886-00…
37 .. _LCD-ILI9342C: https://m5stack.oss-cn-shenzhen.aliyuncs.com/resource/docs/datasheet/core/ILI9342…
38 .. _SPM-1423: https://m5stack.oss-cn-shenzhen.aliyuncs.com/resource/docs/datasheet/core/SPM1423HM4H…
39 .. _RTC-BM8563: https://m5stack.oss-cn-shenzhen.aliyuncs.com/resource/docs/datasheet/core/BM8563_V1…
40 .. _SY7088: https://m5stack.oss-cn-shenzhen.aliyuncs.com/resource/docs/datasheet/core/SY7088-Silerg…
41 .. _PMU-AXP192: https://m5stack.oss-cn-shenzhen.aliyuncs.com/resource/docs/datasheet/core/AXP192_da…
[all …]
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| /Zephyr-latest/boards/nxp/frdm_mcxn947/ |
| D | board.cmake | 11 board_runner_args(linkserver "--core=all")
13 board_runner_args(linkserver "--core=cm33_core0")
29 board_runner_args(linkserver "--core=cm33_core1")
|
| /Zephyr-latest/boards/nordic/nrf5340_audio_dk/doc/ |
| D | index.rst | 24 * nRF5340 dual-core SoC based on the Arm® Cortex®-M33 architecture
46 * A full-featured Arm Cortex-M33F core with DSP instructions,
48 referred to as the **application core**.
49 * A secondary Arm Cortex-M33 core, with a reduced feature set,
50 running at a fixed 64 MHz, referred to as the **network core**.
53 core on the nRF5340 SoC. The ``nrf5340_audio_dk/nrf5340/cpunet`` build target provides
54 support for the network core on the nRF5340 SoC.
|
