Searched refs:core (Results 276 – 300 of 877) sorted by relevance
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11 # even when core is in sleep mode
16 mesh/core.rst
21 # remote core's build, such as the output image's LMA
10 # even when core is in sleep mode
5 Use the Hardware Semaphore (HSEM) to trigger LED blinking from one core to another.
122 This hidden configuration defines that build is targeted for PROCPU (core 0).127 This hidden configuration defines that build is targeted for APPCPU (core 1).
90 # defaults specific for the M7 core92 # Enable cache management features when using M7 core, since these parts
9 - ARM® Cortex® M4F core10 - 16 kB 2-way Associative/Direct-Mapped Cache per core
9 - ARM® Cortex® M4F core10 - 64 kB 2-way Associative/Direct-Mapped Cache per core
6 bool "Ethos-U core driver"10 This option enables the Arm Ethos-U core driver.
41 also run on the network core. The :zephyr_file:`samples/bluetooth/hci_ipc`77 network core application. When :zephyr:code-sample:`bluetooth_hci_ipc` is used as78 network core application, the antenna matrix configuration should be stored in
31 target Xtensa core, based automatically on the details in32 the core-isa.h file. This replaces the previous scheme36 bool "Use crt1.S from core"62 A design trick on multi-core hardware is to map memory twice87 Rate in HZ of the Xtensa core as measured by the value of274 defined in the core architecture code. This gives total control to
11 dual-core MCU, with a 150-MHz Arm Cortex-M4 as the primary application20 The Cortex-M0+ is a primary core on the board's SoC. It starts first and21 enables the CM4 core.137 Only the CM0+ core starts by default after the MCU reset. In order to have138 CM4 core working FW for both cores should be written into Flash. CM0+ FW139 should starts the CM4 core at one point using
28 core-prescaler = <1>; /* CORE_CLK runs at 96MHz */
9 from runners.core import RunnerCaps, ZephyrBinaryRunner
10 from runners.core import ZephyrBinaryRunner
8 # Only use DCD when booting primary core (M7)
8 # Use External Memory Configuration Data (XMCD) by default when booting primary core (M7)
48 add_subdirectory(core)
15 co-processor core on an AMP SoC
18 NXP RT5xx CM33 core
