1# MIMXRT1160-EVK board 2 3# Copyright 2021,2023-2024 NXP 4# SPDX-License-Identifier: Apache-2.0 5 6if BOARD_MIMXRT1160_EVK 7 8# Only use DCD when booting primary core (M7) 9config DEVICE_CONFIGURATION_DATA 10 default y if CPU_CORTEX_M7 11 12config NXP_IMX_EXTERNAL_SDRAM 13 default y if CPU_CORTEX_M7 14 15if SECOND_CORE_MCUX && BOARD_MIMXRT1160_EVK_MIMXRT1166_CM4 16 17config BUILD_OUTPUT_INFO_HEADER 18 default y 19 20DT_CHOSEN_IMAGE_M4 = nxp,m4-partition 21 22# Adjust the offset of the output image if building for RT11xx SOC 23config BUILD_OUTPUT_ADJUST_LMA 24 default "($(dt_chosen_reg_addr_hex,$(DT_CHOSEN_IMAGE_M4)) + \ 25 $(dt_node_reg_addr_hex,/soc/spi@400cc000,1)) - \ 26 $(dt_node_reg_addr_hex,/soc/ocram@20200000)" 27 28endif 29 30config SYS_CLOCK_HW_CYCLES_PER_SEC 31 default 240000000 if BOARD_MIMXRT1160_EVK_MIMXRT1166_CM4 && CORTEX_M_SYSTICK 32 default 600000000 if BOARD_MIMXRT1160_EVK_MIMXRT1166_CM7 && CORTEX_M_SYSTICK 33 34if NETWORKING 35 36config NET_L2_ETHERNET 37 default y if CPU_CORTEX_M7 # No cache memory support is required for driver 38 39config ETH_MCUX_PHY_RESET 40 default y 41 42endif # NETWORKING 43 44endif # BOARD_MIMXRT1160_EVK 45
