Searched refs:core (Results 251 – 275 of 877) sorted by relevance
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| /Zephyr-latest/scripts/west_commands/runners/ |
| D | hifive1.py | 9 from runners.core import RunnerCaps, ZephyrBinaryRunner
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| D | misc.py | 15 from runners.core import RunnerCaps, ZephyrBinaryRunner
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| /Zephyr-latest/boards/nxp/mimxrt1180_evk/ |
| D | Kconfig.defconfig | 8 # Use External Memory Configuration Data (XMCD) by default when booting primary core (M33)
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| /Zephyr-latest/soc/nxp/imxrt/imxrt118x/ |
| D | Kconfig.defconfig | 31 # RT Boot header is only needed on primary core
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| /Zephyr-latest/samples/drivers/mbox_data/ |
| D | sysbuild.cmake | 23 # For these NXP boards the main core application is dependent on
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| /Zephyr-latest/tests/drivers/mbox/mbox_data/ |
| D | sysbuild.cmake | 23 # For these NXP boards the main core application is dependent on
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| /Zephyr-latest/modules/trusted-firmware-m/nordic/ns/ |
| D | CMakeLists.txt | 34 include(${CMAKE_CURRENT_LIST_DIR}/common/core/config_nordic_nrf_spe.cmake)
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| /Zephyr-latest/lib/mem_blocks/ |
| D | Kconfig | 46 bool "Object core statistics for memory blocks"
51 This option integrates the object core statistics framework into
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| /Zephyr-latest/samples/drivers/mbox/ |
| D | README.rst | 35 serial port, one is the application (APP) core another is the network (NET)
36 core:
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| D | sysbuild.cmake | 27 # For these NXP boards the main core application is dependent on
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| /Zephyr-latest/boards/st/nucleo_h755zi_q/doc/ |
| D | index.rst | 113 The dual core nature of STM32H755 SoC requires sharing HW resources between the
116 - **Compilation**: Clock configuration is only accessible to M7 core. M4 core only
130 Applications for the ``nucleo_h755zi_q`` board should be built per core target,
145 The target core is detected automatically.
208 Here is an example for the :zephyr:code-sample:`blinky` application on M4 core.
223 You can debug an application on the Cortex M7 core in the usual way.
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| /Zephyr-latest/samples/bluetooth/direction_finding_connectionless_rx/ |
| D | README.rst | 41 also run on the network core. The :zephyr:code-sample:`bluetooth_hci_ipc` sample
76 network core application. When :zephyr:code-sample:`bluetooth_hci_ipc` is used as the
77 network core application, the antenna matrix configuration should be stored in
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| /Zephyr-latest/boards/arduino/opta/support/ |
| D | openocd_opta_stm32h747xx_m7.cfg | 9 # even when core is in sleep mode
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| /Zephyr-latest/boards/arduino/nicla_vision/support/ |
| D | openocd_arduino_nicla_vision_m7.cfg | 9 # even when core is in sleep mode
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| /Zephyr-latest/soc/snps/nsim/arc_classic/hs/ |
| D | Kconfig.defconfig.hs_smp | 22 # SMP simulation is slower than single core, 1 Mhz seems reasonable match with wallclock
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| /Zephyr-latest/boards/st/stm32h747i_disco/support/ |
| D | openocd_stm32h747i_disco_m7.cfg | 9 # even when core is in sleep mode
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| /Zephyr-latest/boards/arduino/giga_r1/support/ |
| D | openocd_arduino_giga_r1_m7.cfg | 9 # even when core is in sleep mode
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| /Zephyr-latest/boards/intel/adl/doc/ |
| D | index.rst | 8 Alder Lake processor is a 64-bit multi-core processor built on 10-nanometer
65 .. _INTEL_ADL: https://edc.intel.com/content/www/us/en/design/products/platforms/processor-and-core…
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| /Zephyr-latest/doc/project/ |
| D | index.rst | 45 - mainline: The main tree where the core functionality and core features are
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| /Zephyr-latest/boards/qemu/cortex_m3/ |
| D | Kconfig.defconfig | 18 # initialize the PSA Crypto core, so we need to enable the fake TEST_RANDOM_GENERATOR.
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| /Zephyr-latest/doc/services/pm/ |
| D | overview.rst | 9 The architecture and SOC independence is achieved by separating the core PM
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| /Zephyr-latest/boards/nxp/lpcxpresso55s69/doc/ |
| D | index.rst | 15 - LPC55S69 dual core Arm Cortex-M33 microcontroller running at up to 100 MHz
105 only enables the first core.
197 | slot0_ns | 0x00030000[96k] | Second image, core 1 or NS |
257 controller is enabled, the core clock will be reduced to 96MHz. The application
258 may reconfigure clocks after initialization, provided that the core clock is
340 (reset and erase are for recovering a locked core):
351 Building a dual-core image
353 The dual-core samples are run using ``lpcxpresso55s69/lpc55s69/cpu0`` target.
355 and executed on the second core when ``SECOND_CORE_MCUX`` is selected. For
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| /Zephyr-latest/boards/arduino/opta/ |
| D | arduino_opta_stm32h747xx_m4.dts | 15 model = "Arduino OPTA M4 core Programmable Logic Controller";
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| /Zephyr-latest/boards/arm/mps2/ |
| D | CMakeLists.txt | 10 # any binary for CPU0, as this is built by the dual core sample.
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| /Zephyr-latest/arch/nios2/ |
| D | CMakeLists.txt | 37 add_subdirectory(core)
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