| /Zephyr-latest/boards/nxp/common/ |
| D | segger-ecc-systemview.rst | 8 Note that when using SEGGER SystemView or RTT with this SOC, the RTT control
14 The RTT control block address must be provided manually because this SOC
16 control block a fault will occur, provided that ECC is enabled and the RAM
|
| /Zephyr-latest/drivers/watchdog/ |
| D | wdt_litex.c | 67 uint32_t control; in wdt_litex_enable() local
75 control = CONTROL_FEED_BIT | CONTROL_ENABLE_BIT; in wdt_litex_enable()
78 control |= CONTROL_RESET_BIT; in wdt_litex_enable()
81 control |= CONTROL_PAUSE_HALTED_BIT; in wdt_litex_enable()
84 litex_write32(control, config->control_addr); in wdt_litex_enable()
218 .control_addr = DT_INST_REG_ADDR_BY_NAME(n, control), \
|
| /Zephyr-latest/drivers/gpio/ |
| D | Kconfig.renesas_ra_ioport | 12 bool "Support VBATT input control"
14 Enable for Renesas RA which support VBATT input control.
|
| /Zephyr-latest/boards/nxp/imx93_evk/ |
| D | Kconfig | 7 bool "Configure i.MX 93 EVK board mux control during init"
11 int "i.MX 93 EVK board mux control init priority"
|
| /Zephyr-latest/tests/drivers/pinctrl/nrf/ |
| D | Kconfig | 9 bool "Access to pin control configuration"
13 control configuration defined in a device driver.
|
| /Zephyr-latest/drivers/spi/ |
| D | spi_mchp_mss_qspi.c | 349 uint32_t control = mss_qspi_read(s, MSS_QSPI_REG_CONTROL); in mss_qspi_clk_gen_set() local
365 control = mss_qspi_read(s, MSS_QSPI_REG_CONTROL); in mss_qspi_clk_gen_set()
366 control &= ~MSS_QSPI_CONTROL_CLKRATE_MSK; in mss_qspi_clk_gen_set()
367 control |= (val << MSS_QSPI_CONTROL_CLKRATE); in mss_qspi_clk_gen_set()
368 mss_qspi_write(s, control, MSS_QSPI_REG_CONTROL); in mss_qspi_clk_gen_set()
414 uint32_t control = mss_qspi_read(cfg, MSS_QSPI_REG_CONTROL); in mss_qspi_release() local
418 control &= ~MSS_QSPI_CONTROL_ENABLE; in mss_qspi_release()
419 mss_qspi_write(cfg, control, MSS_QSPI_REG_CONTROL); in mss_qspi_release()
556 uint32_t control = 0; in mss_qspi_init() local
560 control &= ~(MSS_QSPI_CONTROL_SAMPLE_MSK); in mss_qspi_init()
[all …]
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| /Zephyr-latest/tests/drivers/pinctrl/gd32/ |
| D | Kconfig | 9 bool "Access to pin control configuration"
13 control configuration defined in a device driver.
|
| /Zephyr-latest/drivers/clock_control/ |
| D | Kconfig.nxp_s32 | 5 bool "NXP S32 clock control driver"
9 Enable support for NXP S32 clock control driver.
|
| /Zephyr-latest/subsys/portability/cmsis_rtos_v2/ |
| D | Kconfig | 19 int "Maximum thread count in CMSIS RTOS V2 application with dynamic control blocks"
24 dynamically allocated control block.
54 be created with dynamically allocated control block.
62 be created with dynamically allocated control block.
70 be created with dynamically allocated control block.
78 be created with dynamically allocated control block.
92 be created with dynamically allocated control block.
106 be created with dynamically allocated control block.
|
| /Zephyr-latest/tests/drivers/spi/spi_loopback/boards/ |
| D | s32z2xxdc2_s32z270_dspi.overlay | 12 nxp,current-reference-control;
18 nxp,current-reference-control;
|
| /Zephyr-latest/doc/hardware/peripherals/ |
| D | video.rst | 39 A video control is accessed and identified by a CID (control identifier). It
40 represents a video control property. Different devices will have different
42 specific. The set/get control functions provide a generic scalable interface
|
| D | reset.rst | 9 Reset controllers are units that control the reset signals to multiple
11 control over their reset input signals, including the ability to assert,
|
| /Zephyr-latest/doc/hardware/pinctrl/ |
| D | index.rst | 6 This is a high-level guide to pin control. See :ref:`pinctrl_api` for API
12 The hardware blocks that control pin multiplexing and pin configuration
23 The way pin control is implemented in hardware is vendor/SoC specific. It is
28 depending on the ``AF`` control bits. Other configuration parameters such as
32 .. figure:: images/hw-cent-control.svg
34 Example of pin control centralized into a single per-pin block
41 .. figure:: images/hw-dist-control.svg
43 Example pin control distributed between peripheral registers and per-pin block
52 Pin control vs. GPIO
57 pin control driver and the GPIO driver. In Zephyr context, the pin control
[all …]
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| /Zephyr-latest/boards/cypress/cy8ckit_062_ble/ |
| D | cy8ckit_062_ble_cy8c6347-pinctrl.dtsi | 9 /* Configure pin control bias mode for uart5 pins */
34 /* Configure pin control bias mode for SPI pins */
|
| /Zephyr-latest/boards/cypress/cy8ckit_062_wifi_bt/ |
| D | cy8ckit_062_wifi_bt_cy8c6247-pinctrl.dtsi | 9 /* Configure pin control bias mode for uart5 pins */
34 /* Configure pin control bias mode for SPI pins */
|
| /Zephyr-latest/drivers/dma/ |
| D | dma_nios2_msgdma.c | 72 uint32_t control; in nios2_msgdma_config() local
108 control = ALTERA_MSGDMA_DESCRIPTOR_CONTROL_TRANSFER_COMPLETE_IRQ_MASK | in nios2_msgdma_config()
117 control); in nios2_msgdma_config()
123 control); in nios2_msgdma_config()
129 control); in nios2_msgdma_config()
|
| /Zephyr-latest/doc/services/ipc/ipc_service/backends/ |
| D | ipc_service_icbmsg.rst | 99 Internally, it uses ICMsg for control messages.
110 * **ICMsg area** - An area reserved by ICMsg instance and used to transfer the control messages.
185 #. The sender sends an ``MSG_DATA`` or ``MSG_BOUND`` control message over ICMsg that contains start…
186 Details about the control message are in the next section.
187 #. The control message travels to the receiver.
188 …ize and data from his ``rx-region`` starting from the block number received in the control message.
190 #. The receiver sends ``MSG_RELEASE_DATA`` or ``MSG_RELEASE_BOUND`` control message over ICMsg cont…
191 (the same as inside received control message).
192 #. The control message travels back to the sender.
193 #. The sender releases the blocks starting from the block number provided in the control message.
[all …]
|
| /Zephyr-latest/boards/quicklogic/qomu/ |
| D | qomu.dts | 74 quicklogic,control-selection = "fabric";
80 quicklogic,control-selection = "fabric";
86 quicklogic,control-selection = "fabric";
|
| /Zephyr-latest/soc/nordic/ |
| D | Kconfig.defconfig | 10 # If the kernel has timer support, enable clock control, except for SoCs
11 # based on the Haltium platform SoCs where clock control is not needed
|
| /Zephyr-latest/snippets/xen_dom0/ |
| D | README.rst | 3 Xen Dom0: universal snippet for XEN control domain
33 directory of this snippet is QEMU Xen control domain example.
39 * build your Zephyr sample/application with ``xen_dom0`` snippet and start it as Xen control domain
51 This will start you a Xen hypervisor with your application as Xen control domain. To make it usable,
|
| /Zephyr-latest/drivers/sensor/microchip/mchp_tach_xec/ |
| D | tach_mchp_xec.c | 39 uint32_t control; member
138 if (data->control & MCHP_TACH_CTRL_EN) { in tach_xec_pm_action()
140 data->control &= (~MCHP_TACH_CTRL_EN); in tach_xec_pm_action()
146 data->control = tach->CONTROL; in tach_xec_pm_action()
|
| /Zephyr-latest/boards/panasonic/pan1781_evb/ |
| D | pan1781_evb-pinctrl.dtsi | 8 /* flow control cannot be used together with i2c0,
21 /* flow control cannot be used together with i2c0,
|
| /Zephyr-latest/tests/drivers/uart/uart_mix_fifo_poll/boards/ |
| D | nrf54h20dk_nrf54h20_common.dtsi | 51 hw-flow-control;
60 hw-flow-control;
|
| /Zephyr-latest/tests/drivers/gpio/gpio_basic_api/boards/ |
| D | intel_ehl_crb.overlay | 9 * GPIO Settings -> GPIO_GPP_B -> GPP_B04 -> PadMode -> GPIO control of the pad
14 * GPIO Settings -> GPIO_GPP_B -> GPP_B23 -> PadMode -> GPIO control of the pad
|
| /Zephyr-latest/tests/bluetooth/shell/boards/ |
| D | cyw920829m2evk_02.overlay | 4 hw-flow-control;
|
