1 /*
2 * Copyright (c) 2022 Microchip Technology Inc.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #define DT_DRV_COMPAT microchip_mpfs_qspi
8
9 #include <zephyr/device.h>
10 #include <zephyr/drivers/spi.h>
11 #include <zephyr/drivers/spi/rtio.h>
12 #include <zephyr/sys/sys_io.h>
13 #include <zephyr/sys/util.h>
14 #include <zephyr/logging/log.h>
15 #include <zephyr/irq.h>
16
17 LOG_MODULE_REGISTER(mss_qspi, CONFIG_SPI_LOG_LEVEL);
18 #include "spi_context.h"
19
20 /*MSS QSPI Register offsets */
21 #define MSS_QSPI_REG_CONTROL (0x00)
22 #define MSS_QSPI_REG_FRAMES (0x04)
23 #define MSS_QSPI_REG_IEN (0x0c)
24 #define MSS_QSPI_REG_STATUS (0x10)
25 #define MSS_QSPI_REG_DIRECT_ACCESS (0x14)
26 #define MSS_QSPI_REG_UPPER_ACCESS (0x18)
27 #define MSS_QSPI_REG_RX_DATA (0x40)
28 #define MSS_QSPI_REG_TX_DATA (0x44)
29 #define MSS_QSPI_REG_X4_RX_DATA (0x48)
30 #define MSS_QSPI_REG_X4_TX_DATA (0x4c)
31 #define MSS_QSPI_REG_FRAMESUP (0x50)
32
33 /* QSPICR bit definitions */
34 #define MSS_QSPI_CONTROL_ENABLE BIT(0)
35 #define MSS_QSPI_CONTROL_MASTER BIT(1)
36 #define MSS_QSPI_CONTROL_XIP BIT(2)
37 #define MSS_QSPI_CONTROL_XIPADDR BIT(3)
38 #define MSS_QSPI_CONTROL_CLKIDLE BIT(10)
39 #define MSS_QSPI_CONTROL_SAMPLE_MSK (3 << 11)
40 #define MSS_QSPI_CONTROL_MODE0 BIT(13)
41 #define MSS_QSPI_CONTROL_MODE_EXQUAD (0x6 << 13)
42 #define MSS_QSPI_CONTROL_MODE_EXDUAL (0x2 << 13)
43 #define MSS_QSPI_CONTROL_MODE12_MSK (3 << 14)
44 #define MSS_QSPI_CONTROL_FLAGSX4 BIT(16)
45 #define MSS_QSPI_CONTROL_CLKRATE_MSK (0xf << 24)
46 #define MSS_QSPI_CONTROL_CLKRATE 24
47
48 /* QSPIFRAMES bit definitions */
49 #define MSS_QSPI_FRAMES_TOTALBYTES_MSK (0xffff << 0)
50 #define MSS_QSPI_FRAMES_TOTALBYTES_MSK (0xffff << 0)
51 #define MSS_QSPI_FRAMES_CMDBYTES_MSK (0x1ff << 16)
52 #define MSS_QSPI_FRAMES_CMDBYTES 16
53 #define MSS_QSPI_FRAMES_QSPI BIT(25)
54 #define MSS_QSPI_FRAMES_IDLE_MSK (0xf << 26)
55 #define MSS_QSPI_FRAMES_FLAGBYTE BIT(30)
56 #define MSS_QSPI_FRAMES_FLAGWORD BIT(31)
57
58 /* QSPIIEN bit definitions */
59 #define MSS_QSPI_IEN_TXDONE BIT(0)
60 #define MSS_QSPI_IEN_RXDONE BIT(1)
61 #define MSS_QSPI_IEN_RXAVAILABLE BIT(2)
62 #define MSS_QSPI_IEN_TXAVAILABLE BIT(3)
63 #define MSS_QSPI_IEN_RXFIFOEMPTY BIT(4)
64 #define MSS_QSPI_IEN_TXFIFOFULL BIT(5)
65 #define MSS_QSPI_IEN_FLAGSX4 BIT(8)
66
67 /* QSPIST bit definitions */
68 #define MSS_QSPI_STATUS_TXDONE BIT(0)
69 #define MSS_QSPI_STATUS_RXDONE BIT(1)
70 #define MSS_QSPI_STATUS_RXAVAILABLE BIT(2)
71 #define MSS_QSPI_STATUS_TXAVAILABLE BIT(3)
72 #define MSS_QSPI_STATUS_RXFIFOEMPTY BIT(4)
73 #define MSS_QSPI_STATUS_TXFIFOFULL BIT(5)
74 #define MSS_QSPI_STATUS_READY BIT(7)
75 #define MSS_QSPI_STATUS_FLAGSX4 BIT(8)
76
77 /* QSPIDA bit definitions */
78 #define MSS_QSPI_DA_EN_SSEL BIT(0)
79 #define MSS_QSPI_DA_OP_SSEL BIT(1)
80 #define MSS_QSPI_DA_EN_SCLK BIT(2)
81 #define MSS_QSPI_DA_OP_SCLK BIT(3)
82 #define MSS_QSPI_DA_EN_SDO_MSK (0xf << 4)
83 #define MSS_QSPI_DA_OP_SDO_MSK (0xf << 8)
84 #define MSS_QSPI_DA_OP_SDATA_MSK (0xf << 12)
85 #define MSS_QSPI_DA_IP_SDI_MSK (0xf << 16)
86 #define MSS_QSPI_DA_IP_SCLK BIT(21)
87 #define MSS_QSPI_DA_IP_SSEL BIT(22)
88 #define MSS_QSPI_DA_IDLE BIT(23)
89 #define MSS_QSPI_RXDATA_MSK (0xff << 0)
90 #define MSS_QSPI_TXDATA_MSK (0xff << 0)
91
92 /* QSPIFRAMESUP bit definitions */
93 #define MSS_QSPI_FRAMESUP_UP_BYTES_MSK (0xFFFF << 16)
94 #define MSS_QSPI_FRAMESUP_LO_BYTES_MSK (0xFFFF << 0)
95
96 /*
97 * Private data structure for an SPI slave
98 */
99 struct mss_qspi_config {
100 mm_reg_t base;
101 void (*irq_config_func)(const struct device *dev);
102 int irq;
103 uint32_t clock_freq;
104 };
105
106 /* Device run time data */
107 struct mss_qspi_data {
108 struct spi_context ctx;
109 };
110
mss_qspi_read(const struct mss_qspi_config * cfg,mm_reg_t offset)111 static inline uint32_t mss_qspi_read(const struct mss_qspi_config *cfg,
112 mm_reg_t offset)
113 {
114 return sys_read32(cfg->base + offset);
115 }
116
mss_qspi_write(const struct mss_qspi_config * cfg,uint32_t val,mm_reg_t offset)117 static inline void mss_qspi_write(const struct mss_qspi_config *cfg,
118 uint32_t val, mm_reg_t offset)
119 {
120 sys_write32(val, cfg->base + offset);
121 }
122
mss_qspi_enable_ints(const struct mss_qspi_config * s)123 static void mss_qspi_enable_ints(const struct mss_qspi_config *s)
124 {
125 uint32_t mask = MSS_QSPI_IEN_TXDONE |
126 MSS_QSPI_IEN_RXDONE |
127 MSS_QSPI_IEN_RXAVAILABLE;
128
129 mss_qspi_write(s, mask, MSS_QSPI_REG_IEN);
130 }
131
mss_qspi_disable_ints(const struct mss_qspi_config * s)132 static void mss_qspi_disable_ints(const struct mss_qspi_config *s)
133 {
134 uint32_t mask = 0;
135
136 mss_qspi_write(s, mask, MSS_QSPI_REG_IEN);
137 }
138
mss_qspi_transmit_x8(const struct device * dev,uint32_t len)139 static inline void mss_qspi_transmit_x8(const struct device *dev, uint32_t len)
140 {
141 const struct mss_qspi_config *s = dev->config;
142 struct mss_qspi_data *data = dev->data;
143 struct spi_context *ctx = &data->ctx;
144 uint32_t count, skips;
145
146 skips = mss_qspi_read(s, MSS_QSPI_REG_CONTROL);
147 skips &= ~MSS_QSPI_CONTROL_FLAGSX4;
148 mss_qspi_write(s, skips, MSS_QSPI_REG_CONTROL);
149 for (count = 0; count < len; ++count) {
150 while (mss_qspi_read(s, MSS_QSPI_REG_STATUS) & MSS_QSPI_STATUS_TXFIFOFULL) {
151 ;
152 }
153 if (spi_context_tx_buf_on(ctx)) {
154 mss_qspi_write(s, ctx->tx_buf[0], MSS_QSPI_REG_TX_DATA);
155 spi_context_update_tx(ctx, 1, 1);
156 }
157 }
158 }
159
mss_qspi_transmit_x32(const struct device * dev,uint32_t len)160 static inline void mss_qspi_transmit_x32(const struct device *dev, uint32_t len)
161 {
162 const struct mss_qspi_config *s = dev->config;
163 struct mss_qspi_data *data = dev->data;
164 struct spi_context *ctx = &data->ctx;
165 uint32_t count, ctrl, wdata;
166
167 ctrl = mss_qspi_read(s, MSS_QSPI_REG_CONTROL);
168 ctrl |= MSS_QSPI_CONTROL_FLAGSX4;
169 mss_qspi_write(s, ctrl, MSS_QSPI_REG_CONTROL);
170 for (count = 0; count < len / 4; ++count) {
171 while (mss_qspi_read(s, MSS_QSPI_REG_STATUS) & MSS_QSPI_STATUS_TXFIFOFULL) {
172 ;
173 }
174 if (spi_context_tx_buf_on(ctx)) {
175 wdata = UNALIGNED_GET((uint32_t *)(ctx->tx_buf));
176 mss_qspi_write(s, wdata, MSS_QSPI_REG_X4_TX_DATA);
177 spi_context_update_tx(ctx, 1, 4);
178 }
179 }
180 }
181
mss_qspi_receive_x32(const struct device * dev,uint32_t len)182 static inline void mss_qspi_receive_x32(const struct device *dev, uint32_t len)
183 {
184 const struct mss_qspi_config *s = dev->config;
185 struct mss_qspi_data *data = dev->data;
186 struct spi_context *ctx = &data->ctx;
187 uint32_t count, ctrl, temp;
188
189 ctrl = mss_qspi_read(s, MSS_QSPI_REG_CONTROL);
190 ctrl |= MSS_QSPI_CONTROL_FLAGSX4;
191 mss_qspi_write(s, ctrl, MSS_QSPI_REG_CONTROL);
192 for (count = 0; count < len / 4; ++count) {
193 while ((mss_qspi_read(s, MSS_QSPI_REG_STATUS) & MSS_QSPI_STATUS_RXFIFOEMPTY)) {
194 ;
195 }
196 if (spi_context_rx_buf_on(ctx)) {
197 temp = mss_qspi_read(s, MSS_QSPI_REG_X4_RX_DATA);
198 UNALIGNED_PUT(temp, (uint32_t *)ctx->rx_buf);
199 spi_context_update_rx(ctx, 1, 4);
200 }
201 }
202 }
203
mss_qspi_receive_x8(const struct device * dev,uint32_t len)204 static inline void mss_qspi_receive_x8(const struct device *dev, uint32_t len)
205 {
206 const struct mss_qspi_config *s = dev->config;
207 struct mss_qspi_data *data = dev->data;
208 struct spi_context *ctx = &data->ctx;
209 uint32_t rdata, count;
210
211 rdata = mss_qspi_read(s, MSS_QSPI_REG_CONTROL);
212 rdata &= ~MSS_QSPI_CONTROL_FLAGSX4;
213 mss_qspi_write(s, rdata, MSS_QSPI_REG_CONTROL);
214 for (count = 0; count < len; ++count) {
215 while (mss_qspi_read(s, MSS_QSPI_REG_STATUS) & MSS_QSPI_STATUS_RXFIFOEMPTY) {
216 ;
217 }
218 if (spi_context_rx_buf_on(ctx)) {
219 rdata = mss_qspi_read(s, MSS_QSPI_REG_RX_DATA);
220 UNALIGNED_PUT(rdata, (uint8_t *)ctx->rx_buf);
221 spi_context_update_rx(ctx, 1, 1);
222 }
223 }
224 }
225
mss_qspi_config_frames(const struct device * dev,uint32_t total_bytes,uint32_t cmd_bytes,bool x8)226 static inline void mss_qspi_config_frames(const struct device *dev,
227 uint32_t total_bytes,
228 uint32_t cmd_bytes, bool x8)
229 {
230 const struct mss_qspi_config *s = dev->config;
231 uint32_t skips;
232
233 mss_qspi_write(s, (total_bytes & MSS_QSPI_FRAMESUP_UP_BYTES_MSK),
234 MSS_QSPI_REG_FRAMESUP);
235 skips = (total_bytes & MSS_QSPI_FRAMESUP_LO_BYTES_MSK);
236 if (cmd_bytes) {
237 skips |= ((cmd_bytes << MSS_QSPI_FRAMES_CMDBYTES) & MSS_QSPI_FRAMES_CMDBYTES_MSK);
238 } else {
239 skips |= ((total_bytes << MSS_QSPI_FRAMES_CMDBYTES) & MSS_QSPI_FRAMES_CMDBYTES_MSK);
240 }
241 if (mss_qspi_read(s, MSS_QSPI_REG_CONTROL) & MSS_QSPI_CONTROL_MODE0) {
242 skips |= MSS_QSPI_FRAMES_QSPI;
243 }
244
245 skips &= ~MSS_QSPI_FRAMES_IDLE_MSK;
246 if (x8) {
247 skips |= MSS_QSPI_FRAMES_FLAGBYTE;
248 } else {
249 skips |= MSS_QSPI_FRAMES_FLAGWORD;
250 }
251
252 mss_qspi_write(s, skips, MSS_QSPI_REG_FRAMES);
253 }
254
mss_qspi_transmit(const struct device * dev)255 static inline void mss_qspi_transmit(const struct device *dev)
256 {
257 const struct mss_qspi_config *s = dev->config;
258 struct mss_qspi_data *data = dev->data;
259 struct spi_context *ctx = &data->ctx;
260 uint32_t total_byte_cnt, cmd_bytes;
261
262 cmd_bytes = spi_context_longest_current_buf(ctx);
263 total_byte_cnt = spi_context_total_tx_len(ctx);
264
265 /*
266 * As per the MSS QSPI IP spec,
267 * The number of command and data bytes are controlled by the frames register
268 * for each SPI sequence. This supports the SPI flash memory read and writes
269 * sequences as below. so configure the cmd and total bytes accordingly.
270 * ---------------------------------------------------------------------
271 * TOTAL BYTES | CMD BYTES | What happens |
272 * ______________________________________________________________________
273 * | | |
274 * 1 | 1 | The SPI core will transmit a single byte |
275 * | | and receive data is discarded |
276 * | | |
277 * 1 | 0 | The SPI core will transmit a single byte |
278 * | | and return a single byte |
279 * | | |
280 * 10 | 4 | The SPI core will transmit 4 command |
281 * | | bytes discarding the receive data and |
282 * | | transmits 6 dummy bytes returning the 6 |
283 * | | received bytes and return a single byte |
284 * | | |
285 * 10 | 10 | The SPI core will transmit 10 command |
286 * | | |
287 * 10 | 0 | The SPI core will transmit 10 command |
288 * | | bytes and returning 10 received bytes |
289 * ______________________________________________________________________
290 */
291 if (!ctx->rx_buf) {
292 if (total_byte_cnt - cmd_bytes) {
293 mss_qspi_config_frames(dev, total_byte_cnt, 0, false);
294 mss_qspi_transmit_x8(dev, cmd_bytes);
295 mss_qspi_transmit_x32(dev, (total_byte_cnt - cmd_bytes));
296
297 } else {
298 mss_qspi_config_frames(dev, total_byte_cnt, cmd_bytes, true);
299 mss_qspi_transmit_x8(dev, cmd_bytes);
300 }
301 } else {
302 mss_qspi_config_frames(dev, total_byte_cnt, cmd_bytes, true);
303 mss_qspi_transmit_x8(dev, cmd_bytes);
304 }
305
306 mss_qspi_enable_ints(s);
307 }
308
mss_qspi_receive(const struct device * dev)309 static inline void mss_qspi_receive(const struct device *dev)
310 {
311 const struct mss_qspi_config *s = dev->config;
312 struct mss_qspi_data *data = dev->data;
313 struct spi_context *ctx = &data->ctx;
314 uint32_t rd_bytes, skips, idx, rdata;
315
316 /*
317 * Point the rx buffer where the actual read data
318 * will be stored
319 */
320 spi_context_update_rx(ctx, 1, ctx->rx_len);
321
322 rd_bytes = spi_context_longest_current_buf(ctx);
323 if (rd_bytes) {
324 if (rd_bytes >= 4) {
325 mss_qspi_receive_x32(dev, rd_bytes);
326 }
327
328 skips = mss_qspi_read(s, MSS_QSPI_REG_CONTROL);
329 skips &= ~MSS_QSPI_CONTROL_FLAGSX4;
330 mss_qspi_write(s, skips, MSS_QSPI_REG_CONTROL);
331 idx = (rd_bytes - (rd_bytes % 4u));
332 for (; idx < rd_bytes; ++idx) {
333 while (mss_qspi_read(s, MSS_QSPI_REG_STATUS) &
334 MSS_QSPI_STATUS_RXFIFOEMPTY) {
335 ;
336 }
337 if (spi_context_rx_buf_on(ctx)) {
338 rdata = mss_qspi_read(s, MSS_QSPI_REG_RX_DATA);
339 UNALIGNED_PUT(rdata, (uint8_t *)ctx->rx_buf);
340 spi_context_update_rx(ctx, 1, 1);
341 }
342 }
343 }
344 }
345
mss_qspi_clk_gen_set(const struct mss_qspi_config * s,const struct spi_config * spi_cfg)346 static inline int mss_qspi_clk_gen_set(const struct mss_qspi_config *s,
347 const struct spi_config *spi_cfg)
348 {
349 uint32_t control = mss_qspi_read(s, MSS_QSPI_REG_CONTROL);
350 uint32_t idx, clkrate, val = 0, speed;
351
352 if (spi_cfg->frequency > s->clock_freq) {
353 speed = s->clock_freq / 2;
354 }
355
356 for (idx = 1; idx < 16; idx++) {
357 clkrate = s->clock_freq / (2 * idx);
358 if (clkrate <= spi_cfg->frequency) {
359 val = idx;
360 break;
361 }
362 }
363
364 if (val) {
365 control = mss_qspi_read(s, MSS_QSPI_REG_CONTROL);
366 control &= ~MSS_QSPI_CONTROL_CLKRATE_MSK;
367 control |= (val << MSS_QSPI_CONTROL_CLKRATE);
368 mss_qspi_write(s, control, MSS_QSPI_REG_CONTROL);
369 } else {
370 return -1;
371 }
372
373 return 0;
374 }
375
mss_qspi_hw_mode_set(const struct mss_qspi_config * s,uint16_t mode)376 static inline int mss_qspi_hw_mode_set(const struct mss_qspi_config *s,
377 uint16_t mode)
378 {
379 uint32_t ctrl = mss_qspi_read(s, MSS_QSPI_REG_CONTROL);
380
381 if ((mode & SPI_MODE_CPHA) && (mode & SPI_MODE_CPOL)) {
382 /* mode 3 */
383 ctrl |= MSS_QSPI_CONTROL_CLKIDLE;
384 } else if (!(mode & SPI_MODE_CPHA) && !(mode & SPI_MODE_CPOL)) {
385 /* mode 0 */
386 ctrl &= ~MSS_QSPI_CONTROL_CLKIDLE;
387 } else {
388 return -1;
389 }
390
391 if ((mode & SPI_LINES_QUAD)) {
392 /* Quad mode */
393 ctrl &= ~(MSS_QSPI_CONTROL_MODE0);
394 ctrl |= (MSS_QSPI_CONTROL_MODE_EXQUAD);
395 } else if ((mode & SPI_LINES_DUAL)) {
396 /* Dual mode */
397 ctrl &= ~(MSS_QSPI_CONTROL_MODE0);
398 ctrl |= (MSS_QSPI_CONTROL_MODE_EXDUAL);
399 } else {
400 /* Normal mode */
401 ctrl &= ~(MSS_QSPI_CONTROL_MODE0);
402 }
403
404 mss_qspi_write(s, ctrl, MSS_QSPI_REG_CONTROL);
405
406 return 0;
407 }
408
mss_qspi_release(const struct device * dev,const struct spi_config * config)409 static int mss_qspi_release(const struct device *dev,
410 const struct spi_config *config)
411 {
412 struct mss_qspi_data *data = dev->data;
413 const struct mss_qspi_config *cfg = dev->config;
414 uint32_t control = mss_qspi_read(cfg, MSS_QSPI_REG_CONTROL);
415
416 mss_qspi_disable_ints(cfg);
417
418 control &= ~MSS_QSPI_CONTROL_ENABLE;
419 mss_qspi_write(cfg, control, MSS_QSPI_REG_CONTROL);
420
421 spi_context_unlock_unconditionally(&data->ctx);
422
423 return 0;
424 }
425
mss_qspi_interrupt(const struct device * dev)426 static void mss_qspi_interrupt(const struct device *dev)
427 {
428 const struct mss_qspi_config *cfg = dev->config;
429 struct mss_qspi_data *data = dev->data;
430 struct spi_context *ctx = &data->ctx;
431
432 int intfield = mss_qspi_read(cfg, MSS_QSPI_REG_STATUS);
433 int ienfield = mss_qspi_read(cfg, MSS_QSPI_REG_IEN);
434
435 if ((intfield & ienfield) == 0) {
436 return;
437 }
438
439 if (intfield & MSS_QSPI_IEN_TXDONE) {
440 mss_qspi_write(cfg, MSS_QSPI_IEN_TXDONE, MSS_QSPI_REG_STATUS);
441 }
442
443 if (intfield & MSS_QSPI_IEN_RXAVAILABLE) {
444 mss_qspi_write(cfg, MSS_QSPI_IEN_RXAVAILABLE, MSS_QSPI_REG_STATUS);
445 mss_qspi_receive(dev);
446 }
447
448 if ((intfield & MSS_QSPI_IEN_RXDONE)) {
449 mss_qspi_write(cfg, MSS_QSPI_IEN_RXDONE, MSS_QSPI_REG_STATUS);
450 spi_context_complete(ctx, dev, 0);
451 }
452
453 if (intfield & MSS_QSPI_IEN_TXAVAILABLE) {
454 mss_qspi_write(cfg, MSS_QSPI_IEN_TXAVAILABLE, MSS_QSPI_REG_STATUS);
455 }
456
457 if (intfield & MSS_QSPI_IEN_RXFIFOEMPTY) {
458 mss_qspi_write(cfg, MSS_QSPI_IEN_RXFIFOEMPTY, MSS_QSPI_REG_STATUS);
459 }
460
461 if (intfield & MSS_QSPI_IEN_TXFIFOFULL) {
462 mss_qspi_write(cfg, MSS_QSPI_IEN_TXFIFOFULL, MSS_QSPI_REG_STATUS);
463 }
464 }
465
mss_qspi_configure(const struct device * dev,const struct spi_config * spi_cfg)466 static int mss_qspi_configure(const struct device *dev,
467 const struct spi_config *spi_cfg)
468 {
469 const struct mss_qspi_config *cfg = dev->config;
470
471 if (spi_cfg->operation & SPI_OP_MODE_SLAVE) {
472 LOG_ERR("Slave mode is not supported\n\r");
473 return -ENOTSUP;
474 }
475
476 if (spi_cfg->operation & SPI_MODE_LOOP) {
477 LOG_ERR("Loop back mode is not supported\n\r");
478 return -ENOTSUP;
479 }
480
481 if (spi_cfg->operation & (SPI_TRANSFER_LSB) ||
482 ((IS_ENABLED(CONFIG_SPI_EXTENDED_MODES) &&
483 (spi_cfg->operation & (SPI_LINES_DUAL |
484 SPI_LINES_QUAD |
485 SPI_LINES_OCTAL))))) {
486 LOG_ERR("Unsupported configuration\n\r");
487 return -ENOTSUP;
488 }
489
490 if (mss_qspi_clk_gen_set(cfg, spi_cfg)) {
491 LOG_ERR("can't set clk divider\n");
492 return -EINVAL;
493 }
494
495 return 0;
496 }
497
mss_qspi_transceive(const struct device * dev,const struct spi_config * spi_cfg,const struct spi_buf_set * tx_bufs,const struct spi_buf_set * rx_bufs,bool async,spi_callback_t cb,void * userdata)498 static int mss_qspi_transceive(const struct device *dev,
499 const struct spi_config *spi_cfg,
500 const struct spi_buf_set *tx_bufs,
501 const struct spi_buf_set *rx_bufs,
502 bool async,
503 spi_callback_t cb,
504 void *userdata)
505 {
506 const struct mss_qspi_config *config = dev->config;
507 struct mss_qspi_data *data = dev->data;
508 struct spi_context *ctx = &data->ctx;
509 int ret = 0;
510
511 spi_context_lock(ctx, async, cb, userdata, spi_cfg);
512 ret = mss_qspi_configure(dev, spi_cfg);
513 if (ret) {
514 goto out;
515 }
516
517 mss_qspi_hw_mode_set(config, spi_cfg->operation);
518 spi_context_buffers_setup(ctx, tx_bufs, rx_bufs,
519 1);
520 mss_qspi_transmit(dev);
521 ret = spi_context_wait_for_completion(ctx);
522 out:
523 spi_context_release(ctx, ret);
524 mss_qspi_disable_ints(config);
525
526 return ret;
527 }
528
mss_qspi_transceive_blocking(const struct device * dev,const struct spi_config * spi_cfg,const struct spi_buf_set * tx_bufs,const struct spi_buf_set * rx_bufs)529 static int mss_qspi_transceive_blocking(const struct device *dev,
530 const struct spi_config *spi_cfg,
531 const struct spi_buf_set *tx_bufs,
532 const struct spi_buf_set *rx_bufs)
533 {
534 return mss_qspi_transceive(dev, spi_cfg, tx_bufs, rx_bufs, false,
535 NULL, NULL);
536 }
537
538 #ifdef CONFIG_SPI_ASYNC
mss_qspi_transceive_async(const struct device * dev,const struct spi_config * spi_cfg,const struct spi_buf_set * tx_bufs,const struct spi_buf_set * rx_bufs,spi_callback_t cb,void * userdata)539 static int mss_qspi_transceive_async(const struct device *dev,
540 const struct spi_config *spi_cfg,
541 const struct spi_buf_set *tx_bufs,
542 const struct spi_buf_set *rx_bufs,
543 spi_callback_t cb,
544 void *userdata)
545 {
546 return mss_qspi_transceive(dev, spi_cfg, tx_bufs, rx_bufs, true,
547 cb, userdata);
548 }
549 #endif /* CONFIG_SPI_ASYNC */
550
mss_qspi_init(const struct device * dev)551 static int mss_qspi_init(const struct device *dev)
552 {
553 const struct mss_qspi_config *cfg = dev->config;
554 struct mss_qspi_data *data = dev->data;
555 unsigned int ret = 0;
556 uint32_t control = 0;
557
558 cfg->irq_config_func(dev);
559
560 control &= ~(MSS_QSPI_CONTROL_SAMPLE_MSK);
561 control &= ~(MSS_QSPI_CONTROL_MODE0);
562 control |= (MSS_QSPI_CONTROL_CLKRATE_MSK);
563 control &= ~(MSS_QSPI_CONTROL_XIP);
564 control |= (MSS_QSPI_CONTROL_CLKIDLE | MSS_QSPI_CONTROL_ENABLE);
565 mss_qspi_write(cfg, control, MSS_QSPI_REG_CONTROL);
566 mss_qspi_disable_ints(cfg);
567 spi_context_unlock_unconditionally(&data->ctx);
568
569 return ret;
570 }
571
572 static DEVICE_API(spi, mss_qspi_driver_api) = {
573 .transceive = mss_qspi_transceive_blocking,
574 #ifdef CONFIG_SPI_ASYNC
575 .transceive_async = mss_qspi_transceive_async,
576 #endif /* CONFIG_SPI_ASYNC */
577 #ifdef CONFIG_SPI_RTIO
578 .iodev_submit = spi_rtio_iodev_default_submit,
579 #endif
580 .release = mss_qspi_release,
581 };
582
583 #define MSS_QSPI_INIT(n) \
584 static void mss_qspi_config_func_##n(const struct device *dev); \
585 \
586 static const struct mss_qspi_config mss_qspi_config_##n = { \
587 .base = DT_INST_REG_ADDR(n), \
588 .irq_config_func = mss_qspi_config_func_##n, \
589 .clock_freq = DT_INST_PROP(n, clock_frequency), \
590 }; \
591 \
592 static struct mss_qspi_data mss_qspi_data_##n = { \
593 SPI_CONTEXT_INIT_LOCK(mss_qspi_data_##n, ctx), \
594 SPI_CONTEXT_INIT_SYNC(mss_qspi_data_##n, ctx), \
595 }; \
596 \
597 SPI_DEVICE_DT_INST_DEFINE(n, mss_qspi_init, NULL, &mss_qspi_data_##n, \
598 &mss_qspi_config_##n, POST_KERNEL, \
599 CONFIG_KERNEL_INIT_PRIORITY_DEVICE, &mss_qspi_driver_api); \
600 \
601 static void mss_qspi_config_func_##n(const struct device *dev) \
602 { \
603 IRQ_CONNECT(DT_INST_IRQN(n), DT_INST_IRQ(n, priority), mss_qspi_interrupt, \
604 DEVICE_DT_INST_GET(n), 0); \
605 irq_enable(DT_INST_IRQN(n)); \
606 }
607
608 DT_INST_FOREACH_STATUS_OKAY(MSS_QSPI_INIT)
609
