Searched refs:cache (Results 101 – 125 of 319) sorted by relevance
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| /Zephyr-latest/scripts/pylib/twister/twisterlib/ |
| D | cmakecache.py | 118 with open(cache_file) as cache:
119 for line_no, line in enumerate(cache):
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| /Zephyr-latest/samples/subsys/usb/mass/boards/ |
| D | rpi_pico.overlay | 37 cache-size = <4096>;
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| /Zephyr-latest/boards/native/nrf_bsim/ |
| D | irq_handler.c | 138 && (_kernel.ready_q.cache) && (_kernel.ready_q.cache != _current)) { in posix_irq_handler()
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| /Zephyr-latest/drivers/display/ |
| D | Kconfig.mcux_dcnano_lcdif | 30 bool "Maintain cache coherency"
33 Maintain cache coherency for LCDIF framebuffer. This is generally
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| D | Kconfig.renesas_ra | 28 # Force display buffers to be aligned to cache line size (64 bytes)
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| /Zephyr-latest/soc/nordic/nrf91/ |
| D | Kconfig | 34 bool "Instruction cache (I-Cache)"
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| /Zephyr-latest/arch/arc/core/ |
| D | CMakeLists.txt | 22 zephyr_library_sources_ifdef(CONFIG_ARCH_CACHE cache.c)
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| /Zephyr-latest/tests/boards/nrf/dmm/boards/ |
| D | nrf5340dk_nrf5340_cpuapp.overlay | 3 dut-cache = &spi1;
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| D | nrf54h20dk_nrf54h20_cpuapp.overlay | 3 dut-cache = &spi120;
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| /Zephyr-latest/scripts/pylib/pytest-twister-harness/ |
| D | .gitignore | 33 .cache
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| /Zephyr-latest/doc/services/ipc/ipc_service/backends/ |
| D | ipc_service_icmsg.rst | 27 * If at least one of the cores uses data cache on shared memory, set the ``dcache-alignment`` value.
29 You can skip it if none of the communication sides is using data cache on shared memory.
111 …led, the shared memory region provided to ICMsg must be aligned according to the cache requirement.
112 If cache is not enabled, the required alignment is 4 bytes.
130 - depends on cache alignment
132 - Padding added to align ``wr_idx`` to the cache alignment.
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| /Zephyr-latest/arch/x86/core/ |
| D | CMakeLists.txt | 22 zephyr_library_sources_ifdef(CONFIG_ARCH_CACHE cache.c)
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| /Zephyr-latest/kernel/include/ |
| D | kernel_offsets.h | 48 GEN_OFFSET_SYM(_ready_q_t, cache);
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| /Zephyr-latest/subsys/settings/ |
| D | Kconfig | 73 bool "NVS name lookup cache"
75 Enable NVS name lookup cache, used to reduce the Settings name
79 int "NVS name lookup cache size"
84 Number of entries in Settings NVS name cache.
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| /Zephyr-latest/drivers/serial/ |
| D | Kconfig.max32 | 23 int "TX cache buffer size"
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| /Zephyr-latest/boards/shields/rk043fn02h_ct/ |
| D | Kconfig.defconfig | 38 # Force display buffers to be aligned to cache line size (32 bytes)
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| /Zephyr-latest/samples/subsys/fs/fs_sample/boards/ |
| D | nrf54l15dk_nrf54l15_cpuapp.overlay | 43 cache-size = <512>;
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| /Zephyr-latest/share/sysbuild/cmake/modules/ |
| D | sysbuild_kconfig.cmake | 26 # to the cache in order for the setting to propagate to images.
67 # We only want to set this in cache it has been defined and is not already there.
76 # Not adding it to CMake cache ensures that a later created sysbuild.conf
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| /Zephyr-latest/doc/connectivity/networking/api/ |
| D | lwm2m.rst | 415 * :kconfig:option:`CONFIG_LWM2M_TLS_SESSION_CACHING` uses session cache when before falling back to…
490 When data cache is enabled for a resource, each write will create a timestamped entry in a cache,
494 Data cache is only supported for resources with a fixed data size.
505 Enable data cache by selecting :kconfig:option:`CONFIG_LWM2M_RESOURCE_DATA_CACHE_SUPPORT`.
507 enable the cache by calling :c:func:`lwm2m_enable_cache` for a given resource. Each resource
512 /* Allocate data cache storage */
514 /* Enable data cache */
518 LwM2M engine have room for four resources that have cache enabled. Limit can be increased by
531 Full content of data cache is written into a payload when any READ, SEND or NOTIFY operation
533 registered for a that resource are ignored when cache is enabled.
[all …]
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| /Zephyr-latest/subsys/net/lib/lwm2m/ |
| D | lwm2m_shell.c | 578 struct lwm2m_time_series_elem *cache; in cmd_cache() local
608 cache = k_malloc(sizeof(struct lwm2m_time_series_elem) * elems); in cmd_cache()
609 if (!cache) { in cmd_cache()
614 rc = lwm2m_enable_cache(&obj_path, cache, elems); in cmd_cache()
618 obj_path.res_inst_id, cache, elems, rc); in cmd_cache()
619 k_free(cache); in cmd_cache()
848 SHELL_CMD_ARG(cache, NULL, LWM2M_HELP_CACHE, cmd_cache, 3, 0),
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| /Zephyr-latest/boards/shields/rk043fn66hs_ctg/ |
| D | Kconfig.defconfig | 41 # Force display buffers to be aligned to cache line size (32 bytes)
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| /Zephyr-latest/dts/x86/intel/ |
| D | lakemont.dtsi | 18 d-cache-line-size = <64>;
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| /Zephyr-latest/boards/nxp/mimxrt1160_evk/ |
| D | Kconfig.defconfig | 37 default y if CPU_CORTEX_M7 # No cache memory support is required for driver
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| /Zephyr-latest/boards/nxp/mimxrt1170_evk/ |
| D | Kconfig.defconfig | 40 default y if CPU_CORTEX_M7 # No cache memory support is required for driver
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| /Zephyr-latest/boards/intel/ish/doc/ |
| D | index.rst | 17 - 16KB instruction cache and 16KB data cache.
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