| /Zephyr-latest/arch/arm64/core/ |
| D | thread.c | 81 return (thread->base.user_options & K_USER) != 0; in is_user()
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| /Zephyr-latest/drivers/adc/ |
| D | adc_ifx_cat1.c | 63 result = Cy_SAR_GetResult32(data->adc_chan_obj[channel_id].adc->base, in _cyhal_adc_event_callback()
83 Cy_SAR_StartConvert(data->adc_obj.base, CY_SAR_START_CONVERT_SINGLE_SHOT); in adc_context_start_sampling()
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| /Zephyr-latest/drivers/i2c/ |
| D | i2c_ambiq.c | 40 uint32_t base; member
347 am_hal_iom_initialize((config->base - IOM0_BASE) / config->size, in i2c_ambiq_init()
445 .base = DT_INST_REG_ADDR(n), \
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| /Zephyr-latest/boards/weact/blackpill_f401ce/doc/ |
| D | index.rst | 10 `here <stm32-base-board-page_>`_ and on `WeAct Github`_.
161 .. _stm32-base-board-page:
162 https://stm32-base.org/boards/STM32F401CEU6-WeAct-Black-Pill-V3.0.html
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| /Zephyr-latest/boards/weact/blackpill_f411ce/doc/ |
| D | index.rst | 10 `here <stm32-base-board-page_>`_ and on `WeAct Github`_.
161 .. _stm32-base-board-page:
162 https://stm32-base.org/boards/STM32F411CEU6-WeAct-Black-Pill-V2.0.html
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| /Zephyr-latest/drivers/spi/ |
| D | spi_mchp_mss_qspi.c | 100 mm_reg_t base; member
114 return sys_read32(cfg->base + offset); in mss_qspi_read()
120 sys_write32(val, cfg->base + offset); in mss_qspi_write()
587 .base = DT_INST_REG_ADDR(n), \
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| D | spi_xlnx_axi_quadspi.c | 87 mm_reg_t base; member
107 return sys_read32(config->base + offset); in xlnx_quadspi_read32()
116 sys_write32(value, config->base + offset); in xlnx_quadspi_write32()
608 .base = DT_INST_REG_ADDR(n), \
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| /Zephyr-latest/drivers/dma/ |
| D | dma_stm32_bdma.h | 42 uint32_t base; member
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| /Zephyr-latest/samples/net/prometheus/src/ |
| D | main.c | 163 prometheus_collector_register_metric(prom_context.collector, &prom_context.counter->base); in main()
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| /Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/ |
| D | l4_i2c1_hsi_lptim1_lse.overlay | 43 * Aim of this part is to provide a base working clock config
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| D | l4_i2c1_sysclk_lptim1_lsi.overlay | 43 * Aim of this part is to provide a base working clock config
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| D | wl_i2c1_sysclk_lptim1_lsi.overlay | 46 * Aim of this part is to provide a base working clock config
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| D | wl_i2c1_hsi_lptim1_lse_adc1_pllp.overlay | 46 * Aim of this part is to provide a base working clock config
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| /Zephyr-latest/cmake/linker/ld/ |
| D | linker_flags.cmake | 5 check_set_linker_property(TARGET linker PROPERTY base
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| /Zephyr-latest/samples/drivers/memc/ |
| D | README.rst | 39 Writing to memory region with base 0x38000000, size 0x800000
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| /Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32u5_devices/boards/ |
| D | core_init.overlay | 69 * Aim of this part is to provide a base working clock config
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| /Zephyr-latest/subsys/llext/ |
| D | llext_link.c | 486 void *base = llext_peek(ldr, shdr->sh_offset); in llext_link() local
488 sys_cache_data_flush_range(base, shdr->sh_size); in llext_link()
489 sys_cache_instr_invd_range(base, shdr->sh_size); in llext_link()
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| /Zephyr-latest/drivers/interrupt_controller/ |
| D | intc_mchp_ecia_xec.c | 54 uintptr_t base; member
471 struct girq_regs *girq = (struct girq_regs *)cfg->base; in xec_girq_isr()
569 .base = DT_REG_ADDR(n), \
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| /Zephyr-latest/dts/arm/nxp/ |
| D | nxp_rt5xx_common.dtsi | 112 * Note that the offsets here are relative to the base address
113 * defined in either nxp_rt5xx_ns.dtsi or nxp_rt5xx.dtsi. The base
413 nxp,dma-otrig-base-address = <RT595_DMA0_OTRIG_BASE>;
414 nxp,dma-itrig-base-address = <RT595_DMA0_ITRIG_BASE>;
425 nxp,dma-otrig-base-address = <RT595_DMA1_OTRIG_BASE>;
426 nxp,dma-itrig-base-address = <RT595_DMA1_ITRIG_BASE>;
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| D | nxp_lpc55S3x_common.dtsi | 155 nxp,dma-otrig-base-address = <LPC55S36_DMA0_OTRIG_BASE>;
156 nxp,dma-itrig-base-address = <LPC55S36_DMA0_ITRIG_BASE>;
167 nxp,dma-otrig-base-address = <LPC55S36_DMA1_OTRIG_BASE>;
168 nxp,dma-itrig-base-address = <LPC55S36_DMA1_ITRIG_BASE>;
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| D | nxp_lpc55S6x_common.dtsi | 205 nxp,dma-otrig-base-address = <LPC55S69_DMA0_OTRIG_BASE>;
206 nxp,dma-itrig-base-address = <LPC55S69_DMA0_ITRIG_BASE>;
217 nxp,dma-otrig-base-address = <LPC55S69_DMA1_OTRIG_BASE>;
218 nxp,dma-itrig-base-address = <LPC55S69_DMA1_ITRIG_BASE>;
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| /Zephyr-latest/scripts/net/ |
| D | README.txt | 73 The sample test script tries to automatically figure out the Zephyr base
78 'docker.conf' exists at the same directory level as the Zephyr base directory.
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| /Zephyr-latest/tests/benchmarks/wait_queues/src/ |
| D | main.c | 296 tag, thread->base.prio); in main()
315 tag, thread->base.prio); in main()
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| /Zephyr-latest/arch/xtensa/core/ |
| D | mpu.c | 886 if (((cur_thread->base.thread_state & _THREAD_DUMMY) != _THREAD_DUMMY) && in arch_mem_domain_partition_add()
908 bool is_user = (thread->base.user_options & K_USER) != 0; in arch_mem_domain_thread_add()
973 if ((thread->base.user_options & K_USER) == 0) { in arch_mem_domain_thread_remove()
978 if ((thread->base.thread_state & _THREAD_DEAD) == 0) { in arch_mem_domain_thread_remove()
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| /Zephyr-latest/kernel/ |
| D | Kconfig.vm | 17 hex "Virtual address space base address"
20 Define the base of the kernel's address space.
22 By default, this is the same as the DT_CHOSEN_Z_SRAM physical base SRAM
37 base addresses being aligned to some common value (which allows
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