| /Zephyr-latest/drivers/dma/ |
| D | dma_stm32u5.c | 49 DMA_TypeDef *dma = (DMA_TypeDef *)(config->base); in dma_stm32_dump_stream_irq()
57 DMA_TypeDef *dma = (DMA_TypeDef *)(config->base); in dma_stm32_clear_stream_irq()
250 DMA_TypeDef *dma = (DMA_TypeDef *)(config->base); in dma_stm32_irq_handler()
350 DMA_TypeDef *dma = (DMA_TypeDef *)dev_config->base; in dma_stm32_configure()
523 DMA_TypeDef *dma = (DMA_TypeDef *)(config->base); in dma_stm32_reload()
560 DMA_TypeDef *dma = (DMA_TypeDef *)(config->base); in dma_stm32_start()
590 DMA_TypeDef *dma = (DMA_TypeDef *)(config->base); in dma_stm32_suspend()
613 DMA_TypeDef *dma = (DMA_TypeDef *)(config->base); in dma_stm32_resume()
632 DMA_TypeDef *dma = (DMA_TypeDef *)(config->base); in dma_stm32_stop()
693 DMA_TypeDef *dma = (DMA_TypeDef *)(config->base); in dma_stm32_get_status()
[all …]
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| /Zephyr-latest/arch/x86/ |
| D | gen_mmu.py | 133 def align_check(base, size, scope=4096): argument
135 if (base % scope) != 0:
136 error("unaligned base address %x" % base)
138 error("Unaligned region size 0x%x for base %x" % (size, base))
525 base = syms[name + "_start"]
531 size = region_end - base
537 (name, base, size, dump_flags(flags)))
542 align_check(base, size, scope)
545 for addr in range(base, base + size, scope):
556 (name, base, size))
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| /Zephyr-latest/drivers/serial/ |
| D | uart_nxp_s32_linflexd.h | 12 LINFLEXD_Type *base; member
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| /Zephyr-latest/scripts/west_commands/sdk/ |
| D | listsdk.cmake | 6 set(ZEPHYR_BASE $ENV{ZEPHYR_BASE} CACHE PATH "Zephyr base")
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| /Zephyr-latest/drivers/watchdog/ |
| D | wdt_tco.c | 14 #define BASE(d) ((struct tco_config *)(d)->config)->base
63 io_port_t base; member
246 LOG_DBG("Using 0x%04x as TCOBA", config->base); in wdt_init()
268 .base = DT_INST_REG_ADDR(0),
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| /Zephyr-latest/drivers/can/ |
| D | can_mcux_mcan.c | 25 mm_reg_t base; member
39 return can_mcan_sys_read_reg(mcux_config->base, reg, val); in mcux_mcan_read_reg()
47 return can_mcan_sys_write_reg(mcux_config->base, reg, val); in mcux_mcan_write_reg()
205 .base = CAN_MCAN_DT_INST_MCAN_ADDR(n), \
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| D | can_sam.c | 22 mm_reg_t base; member
36 return can_mcan_sys_read_reg(sam_config->base, reg, val); in can_sam_read_reg()
44 return can_mcan_sys_write_reg(sam_config->base, reg, val); in can_sam_write_reg()
178 .base = CAN_MCAN_DT_INST_MCAN_ADDR(inst), \
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| D | can_sam0.c | 23 mm_reg_t base; member
38 return can_mcan_sys_read_reg(sam_config->base, reg, val); in can_sam0_read_reg()
60 return can_mcan_sys_write_reg(sam_config->base, reg, val); in can_sam0_write_reg()
212 .base = CAN_MCAN_DT_INST_MCAN_ADDR(inst), \
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| /Zephyr-latest/subsys/net/lib/prometheus/ |
| D | formatter.c | 122 CONTAINER_OF(metric, struct prometheus_counter, base); in prometheus_format_one_metric()
142 CONTAINER_OF(metric, struct prometheus_gauge, base); in prometheus_format_one_metric()
162 CONTAINER_OF(metric, struct prometheus_histogram, base); in prometheus_format_one_metric()
198 CONTAINER_OF(metric, struct prometheus_summary, base); in prometheus_format_one_metric()
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| /Zephyr-latest/drivers/dai/intel/dmic/ |
| D | dmic_nhlt.c | 57 static void dai_dmic_write_coeff(const struct dai_intel_dmic *dmic, uint32_t base, in dai_dmic_write_coeff() argument
65 dai_dmic_write(dmic, base, *coeff++); in dai_dmic_write_coeff()
66 base += sizeof(uint32_t); in dai_dmic_write_coeff()
76 dai_dmic_write(dmic, base, coeff_val); in dai_dmic_write_coeff()
77 base += sizeof(uint32_t); in dai_dmic_write_coeff()
603 static void configure_fir(struct dai_intel_dmic *dmic, const uint32_t base, in configure_fir() argument
612 dai_dmic_write(dmic, base + FIR_CONFIG, val); in configure_fir()
619 dai_dmic_write(dmic, base + FIR_CONTROL, val); in configure_fir()
623 dai_dmic_write(dmic, base + DC_OFFSET_LEFT, fir_cfg->dc_offset_left); in configure_fir()
624 dai_dmic_write(dmic, base + DC_OFFSET_RIGHT, fir_cfg->dc_offset_right); in configure_fir()
[all …]
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| /Zephyr-latest/lib/acpi/ |
| D | acpi.c | 671 uintptr_t offset, uintptr_t base, uint32_t madt_len) in acpi_get_subtable_entry_num() argument
680 subtable = ACPI_ADD_PTR(ACPI_SUBTABLE_HEADER, base, offset); in acpi_get_subtable_entry_num()
693 uintptr_t base = POINTER_TO_UINT(madt); in acpi_madt_entry_get() local
701 subtable = ACPI_ADD_PTR(ACPI_SUBTABLE_HEADER, base, offset); in acpi_madt_entry_get()
706 *num_inst = acpi_get_subtable_entry_num(type, subtable, offset, base, in acpi_madt_entry_get()
712 subtable = ACPI_ADD_PTR(ACPI_SUBTABLE_HEADER, base, offset); in acpi_madt_entry_get()
721 uintptr_t base = POINTER_TO_UINT(dmar); in acpi_dmar_entry_get() local
730 subtable = ACPI_ADD_PTR(ACPI_DMAR_HEADER, base, offset); in acpi_dmar_entry_get()
737 subtable = ACPI_ADD_PTR(ACPI_DMAR_HEADER, base, offset); in acpi_dmar_entry_get()
845 uintptr_t base; in acpi_drhd_get() local
[all …]
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| /Zephyr-latest/drivers/ipm/ |
| D | ipm_mhu.c | 17 (((const struct ipm_mhu_device_config * const)(dev)->config)->base))
177 .base = (uint8_t *)DT_INST_REG_ADDR(0),
208 .base = (uint8_t *)DT_INST_REG_ADDR(1),
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| /Zephyr-latest/include/zephyr/data/ |
| D | jwt.h | 34 char *base; member
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| /Zephyr-latest/drivers/sdhc/ |
| D | sam_hsmci.c | 66 Hsmci *base; member
81 Hsmci *hsmci = config->base; in sam_hsmci_reset()
119 Hsmci *hsmci = config->base; in sam_hsmci_set_io()
218 Hsmci *hsmci = config->base; in sam_hsmci_init()
249 Hsmci *hsmci = config->base; in sam_hsmci_card_busy()
484 Hsmci *hsmci = config->base; in sam_hsmci_request_inner()
606 Hsmci *hsmci = config->base; in sam_hsmci_abort()
631 Hsmci *hsmci = config->base; in sam_hsmci_request()
675 .base = (Hsmci *)DT_INST_REG_ADDR(N), \
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| /Zephyr-latest/include/zephyr/arch/x86/ |
| D | memmap.h | 51 uint64_t base; member
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| /Zephyr-latest/include/zephyr/drivers/misc/coresight/ |
| D | stmesp.h | 178 STMESP_Type *const base = (STMESP_Type *const)DT_REG_ADDR(DT_NODELABEL(stmesp)); in stmesp_get_port() local
180 *port = &base[idx]; in stmesp_get_port()
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| /Zephyr-latest/drivers/clock_control/ |
| D | clock_control_mcux_pcc.c | 29 #define MAKE_PCC_REGADDR(base, offset) ((base) + (offset)) argument
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| /Zephyr-latest/subsys/bluetooth/audio/ |
| D | bap_broadcast_sink.c | 504 static int update_recv_state_base_copy_meta(const struct bt_bap_base *base, in update_recv_state_base_copy_meta() argument
509 err = bt_bap_base_foreach_subgroup(base, base_subgroup_meta_cb, param); in update_recv_state_base_copy_meta()
519 const struct bt_bap_base *base) in update_recv_state_base() argument
532 err = update_recv_state_base_copy_meta(base, &mod_src_param); in update_recv_state_base()
710 static int store_base_info(struct bt_bap_broadcast_sink *sink, const struct bt_bap_base *base) in store_base_info() argument
717 ret = bt_bap_base_get_pres_delay(base); in store_base_info()
727 ret = bt_bap_base_foreach_subgroup(base, base_subgroup_cb, &data); in store_base_info()
760 static int base_get_bis_count(const struct bt_bap_base *base) in base_get_bis_count() argument
765 err = bt_bap_base_foreach_subgroup(base, base_subgroup_bis_count_cb, &bis_cnt); in base_get_bis_count()
777 const struct bt_bap_base *base = bt_bap_base_get_base_from_ad(data); in pa_decode_base() local
[all …]
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| /Zephyr-latest/drivers/dai/intel/hda/ |
| D | hda.h | 14 #define dai_base(dai) dai->plat_data.base
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| /Zephyr-latest/drivers/pinctrl/ |
| D | pinctrl_npcx.c | 24 uintptr_t base; member
30 .base = DT_REG_ADDR(node_id), \
92 reg = pwm_pinctrl_cfg[i].base; in npcx_periph_pwm_drive_mode_configure()
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| /Zephyr-latest/drivers/pwm/ |
| D | pwm_sifive.c | 21 #define PWM_REG(z_config, _offset) ((mem_addr_t) ((z_config)->base + _offset))
54 uint32_t base; member
220 .base = DT_INST_REG_ADDR(n), \
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| /Zephyr-latest/drivers/pcie/endpoint/ |
| D | pcie_ep_iproc_msi.c | 74 pcie_write32(msi_num, &cfg->base->paxb_pcie_sys_msi_req); in iproc_pcie_generate_msi()
180 data = pcie_read32(&cfg->base->paxb_pcie_cfg_intr_status); in iproc_pcie_func_mask_isr()
186 &cfg->base->paxb_pcie_cfg_intr_clear); in iproc_pcie_func_mask_isr()
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| /Zephyr-latest/arch/arm/core/mpu/ |
| D | arm_core_mpu.c | 250 uintptr_t base = (uintptr_t)thread->stack_obj; in z_arm_configure_dynamic_mpu_regions() local
252 (thread->stack_info.start - base); in z_arm_configure_dynamic_mpu_regions()
257 dynamic_regions[region_num].start = base; in z_arm_configure_dynamic_mpu_regions()
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| /Zephyr-latest/arch/arm/core/cortex_a_r/ |
| D | thread.c | 69 if ((thread->base.user_options & K_FP_REGS) != 0) { in arch_new_thread()
83 if ((thread->base.user_options & K_USER) != 0) { in arch_new_thread()
121 if ((thread->base.user_options & K_FP_REGS) != 0) { in arch_new_thread()
397 thread->base.user_options &= ~K_FP_REGS; in arch_float_disable()
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| /Zephyr-latest/samples/subsys/ipc/ipc_service/static_vrings/ |
| D | Kconfig | 11 needs to be aware of size or base address of secondary image
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