| /Zephyr-latest/drivers/mipi_dbi/ |
| D | mipi_dbi_nxp_flexio_lcdif.c | 120 static void flexio_lcdif_write_data_array(FLEXIO_MCULCD_Type *base, in flexio_lcdif_write_data_array() argument
128 FLEXIO_Type *flexioBase = base->flexioBase; in flexio_lcdif_write_data_array()
131 base->setRSPin(true, base->userData); in flexio_lcdif_write_data_array()
133 if (kFLEXIO_MCULCD_6800 == base->busType) { in flexio_lcdif_write_data_array()
134 base->setRDWRPin(false, base->userData); in flexio_lcdif_write_data_array()
138 FLEXIO_MCULCD_SetSingleBeatWriteConfig(base); in flexio_lcdif_write_data_array()
143 flexioBase->SHIFTBUF[base->txShifterStartIndex] = data8Bit[i]; in flexio_lcdif_write_data_array()
146 while (0U == ((1UL << base->timerIndex) & flexioBase->TIMSTAT)) { in flexio_lcdif_write_data_array()
150 flexioBase->TIMSTAT = 1UL << base->timerIndex; in flexio_lcdif_write_data_array()
154 FLEXIO_MCULCD_ClearSingleBeatWriteConfig(base); in flexio_lcdif_write_data_array()
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| /Zephyr-latest/drivers/serial/ |
| D | uart_nxp_s32_linflexd.c | 50 linflexd_ier = sys_read32(POINTER_TO_UINT(&config->base->LINIER)); in uart_nxp_s32_poll_out()
56 sys_write32(linflexd_ier, POINTER_TO_UINT(&config->base->LINIER)); in uart_nxp_s32_poll_out()
71 linflexd_ier = sys_read32(POINTER_TO_UINT(&config->base->LINIER)); in uart_nxp_s32_poll_in()
78 sys_write32(linflexd_ier, POINTER_TO_UINT(&config->base->LINIER)); in uart_nxp_s32_poll_in()
208 linflexd_ier = sys_read32(POINTER_TO_UINT(&config->base->LINIER)); in uart_nxp_s32_irq_err_enable()
213 sys_write32(linflexd_ier, POINTER_TO_UINT(&config->base->LINIER)); in uart_nxp_s32_irq_err_enable()
221 linflexd_ier = sys_read32(POINTER_TO_UINT(&config->base->LINIER)); in uart_nxp_s32_irq_err_disable()
226 sys_write32(linflexd_ier, POINTER_TO_UINT(&config->base->LINIER)); in uart_nxp_s32_irq_err_disable()
370 .base = (LINFLEXD_Type *)DT_INST_REG_ADDR(n), \
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| /Zephyr-latest/drivers/pcie/host/ |
| D | shell.c | 177 uint32_t base; in show_capabilities() local
183 base = pcie_get_cap(bdf, cap_id2str->id); in show_capabilities()
184 if (base != 0) { in show_capabilities()
196 base = pcie_get_ext_cap(bdf, cap_id2str->id); in show_capabilities()
197 if (base != 0) { in show_capabilities()
208 uint32_t base; in show_vc() local
213 base = pcie_vc_cap_lookup(bdf, ®s); in show_vc()
214 if (base == 0) { in show_vc()
228 pcie_vc_load_resources_regs(bdf, base, res_regs, in show_vc()
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| /Zephyr-latest/drivers/display/ |
| D | display_mcux_dcnano_lcdif.c | 24 LCDIF_Type *base; member
107 LCDIF_SetFrameBufferStride(config->base, 0, in mcux_dcnano_lcdif_write()
109 LCDIF_SetFrameBufferAddr(config->base, 0, in mcux_dcnano_lcdif_write()
111 LCDIF_SetFrameBufferConfig(config->base, 0, &data->fb_config); in mcux_dcnano_lcdif_write()
203 status = LCDIF_GetAndClearInterruptPendingFlags(config->base); in mcux_dcnano_lcdif_isr()
227 LCDIF_Init(config->base); in mcux_dcnano_lcdif_init()
229 LCDIF_DpiModeSetConfig(config->base, 0, &config->dpi_config); in mcux_dcnano_lcdif_init()
231 LCDIF_EnableInterrupts(config->base, kLCDIF_Display0FrameDoneInterrupt); in mcux_dcnano_lcdif_init()
302 .base = (LCDIF_Type *) DT_INST_REG_ADDR(n), \
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| /Zephyr-latest/kernel/ |
| D | mailbox.c | 168 tx_msg = (struct k_mbox_msg *)sending_thread->base.swap_data; in mbox_message_dispose()
178 if ((sending_thread->base.thread_state & _THREAD_DUMMY) != 0U) { in mbox_message_dispose()
223 sending_thread->base.swap_data = tx_msg; in mbox_message_put()
231 rx_msg = (struct k_mbox_msg *)receiving_thread->base.swap_data; in mbox_message_put()
249 if ((sending_thread->base.thread_state & _THREAD_DUMMY) in mbox_message_put()
279 if ((sending_thread->base.thread_state & _THREAD_DUMMY) != 0U) { in mbox_message_put()
324 async->thread.prio = arch_current_thread()->base.prio; in k_mbox_async_put()
399 tx_msg = (struct k_mbox_msg *)sending_thread->base.swap_data; in k_mbox_get()
428 arch_current_thread()->base.swap_data = rx_msg; in k_mbox_get()
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| /Zephyr-latest/drivers/watchdog/ |
| D | wdt_andes_atcwdt200.c | 86 uintptr_t base; member
103 uint32_t wdt_addr = ((const struct wdt_atcwdt200_config *)(dev->config))->base; in wdt_counter_cb()
125 uint32_t wdt_addr = ((const struct wdt_atcwdt200_config *)(dev->config))->base; in wdt_atcwdt200_set_max_timeout()
150 uint32_t wdt_addr = ((const struct wdt_atcwdt200_config *)(dev->config))->base; in wdt_atcwdt200_disable()
173 uint32_t wdt_addr = ((const struct wdt_atcwdt200_config *)(dev->config))->base; in wdt_atcwdt200_setup()
240 uint32_t wdt_addr = ((const struct wdt_atcwdt200_config *)(dev->config))->base; in wdt_atcwdt200_install_timeout()
292 uint32_t wdt_addr = ((const struct wdt_atcwdt200_config *)(dev->config))->base; in wdt_atcwdt200_feed()
331 .base = DT_INST_REG_ADDR(0),
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| D | wdt_gecko.c | 34 WDOG_TypeDef *base; member
94 WDOG_TypeDef *wdog = config->base; in wdt_gecko_setup()
131 WDOG_TypeDef *wdog = config->base; in wdt_gecko_disable()
216 WDOG_TypeDef *wdog = config->base; in wdt_gecko_feed()
233 WDOG_TypeDef *wdog = config->base; in wdt_gecko_isr()
286 .base = (WDOG_TypeDef *) \
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| /Zephyr-latest/drivers/ethernet/nxp_enet/ |
| D | eth_nxp_enet.c | 98 ENET_Type *base; member
225 ret = ENET_SendFrame(data->base, &data->enet_handle, data->tx_frame_buf, in eth_nxp_enet_tx()
230 ENET_ReclaimTxDescriptor(data->base, &data->enet_handle, RING_ID); in eth_nxp_enet_tx()
291 ENET_SetMacAddr(data->base, data->mac_addr); in eth_nxp_enet_set_config()
304 ENET_AddMulticastGroup(data->base, in eth_nxp_enet_set_config()
307 ENET_LeaveMulticastGroup(data->base, in eth_nxp_enet_set_config()
377 status = ENET_ReadFrame(data->base, &data->enet_handle, in eth_nxp_enet_rx()
431 status = ENET_ReadFrame(data->base, &data->enet_handle, NULL, in eth_nxp_enet_rx()
457 ENET_EnableInterrupts(data->base, kENET_RxFrameInterrupt); in eth_nxp_enet_rx_thread()
503 ENET_SetMII(data->base, speed, duplex);
[all …]
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| /Zephyr-latest/kernel/include/ |
| D | wait_q.h | 25 RB_FOR_EACH_CONTAINER(&(wq)->waitq.tree, thread_ptr, base.qnode_rb)
45 base.qnode_dlist)
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| D | ksched.h | 146 __ASSERT(arch_current_thread()->base.sched_locked != 1U, ""); in z_sched_lock()
148 --arch_current_thread()->base.sched_locked; in z_sched_lock()
155 __ASSERT_NO_MSG(thread->base.pended_on); in pended_on_thread()
157 return thread->base.pended_on; in pended_on_thread()
165 thread->base.pended_on = NULL; in unpend_thread_no_timeout()
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| /Zephyr-latest/drivers/sensor/nxp/qdec_mcux/ |
| D | qdec_mcux.c | 23 ENC_Type *base; member
64 WRITE_BIT(config->base->CTRL, ENC_CTRL_PH1_SHIFT, val->val1); in qdec_mcux_attr_set()
103 data->position = ENC_GetPositionValue(config->base); in qdec_mcux_fetch()
174 .base = (ENC_Type *)DT_INST_REG_ADDR(n), \
199 ENC_Init(config->base, &data->qdec_config); \
202 ENC_DoSoftwareLoadInitialPositionValue(config->base); \
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| /Zephyr-latest/subsys/jwt/ |
| D | jwt_legacy_rsa.c | 48 res = mbedtls_sha256(builder->base, builder->buf - builder->base, hash, 0); in jwt_sign_impl()
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| /Zephyr-latest/drivers/spi/ |
| D | spi_sifive.h | 21 #define SPI_REG(dev, offset) ((mem_addr_t) (SPI_CFG(dev)->base + (offset)))
72 uint32_t base; member
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| /Zephyr-latest/samples/net/cloud/tagoio_http_post/src/ |
| D | main.c | 38 #define base 1000.00f in collect_data() macro
44 temp /= base; in collect_data()
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| /Zephyr-latest/soc/nxp/kinetis/k6x/ |
| D | README.txt | 1 Notes on the FSL FRDM K64F SRAM base address and size
5 standard ARMv7-M SRAM base address of 0x20000000 is supported.
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| /Zephyr-latest/include/zephyr/sys/ |
| D | timeutil.h | 147 struct timeutil_sync_instant base; member
218 const struct timeutil_sync_instant *base);
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| /Zephyr-latest/tests/ztest/zexpect/ |
| D | CMakeLists.txt | 6 project(base) project
11 project(base) project
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| /Zephyr-latest/tests/arch/x86/info/src/ |
| D | memmap.c | 56 entry->base, entry->base + entry->length - 1, in memmap()
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| /Zephyr-latest/subsys/net/ip/ |
| D | net_stats.c | 437 if (entry->base.collector != iface->collector) { in register_prometheus_metrics()
442 &entry->base); in register_prometheus_metrics()
447 if (entry->base.collector != iface->collector) { in register_prometheus_metrics()
452 &entry->base); in register_prometheus_metrics()
457 if (entry->base.collector != iface->collector) { in register_prometheus_metrics()
462 &entry->base); in register_prometheus_metrics()
467 if (entry->base.collector != iface->collector) { in register_prometheus_metrics()
472 &entry->base); in register_prometheus_metrics()
503 CONTAINER_OF(metric, struct prometheus_counter, base); in net_stats_prometheus_scrape()
515 CONTAINER_OF(metric, struct prometheus_gauge, base); in net_stats_prometheus_scrape()
[all …]
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| /Zephyr-latest/drivers/input/ |
| D | input_npcx_kbd.c | 29 struct kbs_reg *base; member
77 struct kbs_reg *const inst = config->base; in npcx_kbd_drive_column()
109 struct kbs_reg *const inst = config->base; in npcx_kbd_read_row()
145 struct kbs_reg *const inst = config->base; in npcx_kbd_init()
219 .base = (struct kbs_reg *)DT_INST_REG_ADDR(0),
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| /Zephyr-latest/drivers/pwm/ |
| D | pwm_npcx.c | 39 struct pwm_reg *base; member
56 struct pwm_reg *inst = config->base; in pwm_npcx_configure()
89 struct pwm_reg *inst = config->base; in pwm_npcx_set_cycles()
175 struct pwm_reg *const inst = config->base; in pwm_npcx_init()
224 .base = (struct pwm_reg *)DT_INST_REG_ADDR(inst), \
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| /Zephyr-latest/soc/snps/arc_iot/ |
| D | linker.ld | 14 * SRAM base address and size
29 /* Instruction Closely Coupled Memory (ICCM) base address and size */
37 * DCCM base address and size. DCCM is the data memory.
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| /Zephyr-latest/soc/nxp/imx/imx7d/ |
| D | soc_clk_freq.c | 12 uint32_t get_pwm_clock_freq(PWM_Type *base) in get_pwm_clock_freq() argument
18 switch ((uint32_t)base) { in get_pwm_clock_freq()
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| /Zephyr-latest/share/zephyr-package/cmake/ |
| D | ZephyrConfig.cmake | 9 # First check to see if user has provided a Zephyr base manually.
10 # Set Zephyr base to environment setting.
91 set(ZEPHYR_BASE ${ZEPHYR_BASE} CACHE PATH "Zephyr base")
92 include_boilerplate("Zephyr base")
97 include_boilerplate("Zephyr base (cached)")
108 # Find out the current Zephyr base.
116 set(ZEPHYR_BASE ${CURRENT_ZEPHYR_DIR} CACHE PATH "Zephyr base")
124 set(ZEPHYR_BASE ${CURRENT_ZEPHYR_DIR} CACHE PATH "Zephyr base")
147 set(ZEPHYR_BASE ${CURRENT_ZEPHYR_DIR} CACHE PATH "Zephyr base")
158 set(ZEPHYR_BASE ${CURRENT_ZEPHYR_DIR} CACHE PATH "Zephyr base")
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| /Zephyr-latest/arch/arm/core/mpu/ |
| D | nxp_mpu.c | 89 uint32_t region_base = region_conf->base; in region_init()
150 .base = (reg).dt_addr, \
209 const k_mem_partition_attr_t *attr, uint32_t base, uint32_t size) in get_region_attr_from_mpu_partition_info() argument
214 (void) base; in get_region_attr_from_mpu_partition_info()
231 region_conf.base = new_region->start; in mpu_configure_region()
266 added_sram_region.base = p_region->start + p_region->size; in mpu_sram_partitioning()
285 adjusted_sram_region.base = in mpu_sram_partitioning()
286 mpu_config.mpu_regions[mpu_config.sram_region].base; in mpu_sram_partitioning()
552 uint32_t base = mpu_region_get_base(i); in arm_core_mpu_mem_partition_config_update() local
554 if (base != partition->start) { in arm_core_mpu_mem_partition_config_update()
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