1 /*
2  * Copyright (c) 2018 SiFive Inc.
3  *
4  * SPDX-License-Identifier: Apache-2.0
5  */
6 
7 #ifndef _SPI_SIFIVE__H
8 #define _SPI_SIFIVE__H
9 
10 #include "spi_context.h"
11 
12 #include <zephyr/sys/sys_io.h>
13 #include <zephyr/device.h>
14 #include <zephyr/drivers/spi.h>
15 #include <zephyr/drivers/spi/rtio.h>
16 #include <zephyr/drivers/pinctrl.h>
17 
18 #define SPI_CFG(dev) ((struct spi_sifive_cfg *) ((dev)->config))
19 #define SPI_DATA(dev) ((struct spi_sifive_data *) ((dev)->data))
20 
21 #define SPI_REG(dev, offset) ((mem_addr_t) (SPI_CFG(dev)->base + (offset)))
22 
23 /* Register Offsets */
24 #define REG_SCKDIV  0x000
25 #define REG_SCKMODE 0x004
26 #define REG_CSID    0x010
27 #define REG_CSDEF   0x014
28 #define REG_CSMODE  0x018
29 #define REG_DELAY0  0x028
30 #define REG_DELAY1  0x02C
31 #define REG_FMT     0x040
32 #define REG_TXDATA  0x048
33 #define REG_RXDATA  0x04C
34 #define REG_TXMARK  0x050
35 #define REG_RXMARK  0x054
36 #define REG_FCTRL   0x060
37 #define REG_FFMT    0x064
38 #define REG_IE      0x070
39 #define REG_IP      0x074
40 
41 /* Masks */
42 #define SF_SCKDIV_DIV_MASK  (0xFFF << 0)
43 #define SF_FMT_PROTO_MASK   (0x3 << 0)
44 #define SF_FMT_LEN_MASK     (0xF << 16)
45 
46 /* Offsets */
47 #define SF_SCKMODE_POL  1
48 #define SF_SCKMODE_PHA  0
49 
50 #define SF_FMT_LEN      16
51 #define SF_FMT_ENDIAN   2
52 
53 #define SF_FCTRL_EN 0
54 
55 /* Values */
56 #define SF_CSMODE_AUTO  0
57 #define SF_CSMODE_HOLD  2
58 #define SF_CSMODE_OFF   3
59 
60 #define SF_FMT_PROTO_SINGLE	0
61 
62 #define SF_TXDATA_FULL  (1 << 31)
63 #define SF_RXDATA_EMPTY (1 << 31)
64 
65 /* Structure Declarations */
66 
67 struct spi_sifive_data {
68 	struct spi_context ctx;
69 };
70 
71 struct spi_sifive_cfg {
72 	uint32_t base;
73 	uint32_t f_sys;
74 	const struct pinctrl_dev_config *pcfg;
75 };
76 
77 #endif /* _SPI_SIFIVE__H */
78