| /Zephyr-latest/boards/renesas/voice_ra4e1/doc/ |
| D | index.rst | 7 Application Engineers, Field Application Engineers, and for Business Development opportunities. The
8 primary purpose is to evaluate the functionality of projects developed by Ecosystem Partners, and to
10 48pin package as the core logic device, with QSPI flash, OPAMP and power devices chosen from the
30 - PMOD: 1 Digilent PMOD connectors, supporting UART, SPI and I2C configurations.
31 - Microphones: 1 I2S MEMS digital microphones and 2 MEMS analog microphones, distance between
34 - LEDs: Five LEDs, D2 (Red), D3 (Green) and D4 (Blue) configurable by user, D5 (Blue) as a 3.3V pow…
36 - Buttons: One RESET button (S2), and one USER button (S1).
38 - USB: Micro USB-B (J6) for power input and J-Link On-Board function, USB-C (J1) for power input and
55 Programming and Debugging
59 built, flashed, and debugged in the usual way. See
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| /Zephyr-latest/boards/nxp/frdm_mcxw72/doc/ |
| D | index.rst | 9 multiprotocol radio subsystem supporting Matter, Thread, Zigbee and
10 Bluetooth LE. The independent radio subsystem, with a dedicated core and
11 memory, offloads the main CPU, preserving it for the primary application and
22 For more information about the MCXW72 SoC and FRDM-MCXW72 board, see:
59 Programming and Debugging
62 Build and flash applications as usual (see :ref:`build_an_application` and
68 A debug probe is used for both flashing and debugging the board. This board is
74 Linkserver is the default runner for this board, and supports the factory
100 Connect a USB cable from your PC to J14, and use the serial terminal of your choice
118 Open a serial terminal, reset the board (press the RESET button), and you should
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| /Zephyr-latest/samples/drivers/clock_control_litex/ |
| D | README.rst | 11 …lock Manager (MMCM) module to generate up to 7 clocks with defined phase, frequency and duty cycle.
16 * SoC configuration with VexRiscv soft CPU and Xilinx 7-series MMCM interface in LiteX (S7MMCM modu…
41 …ion defines 2 clock outputs: ``clk0`` and ``clk1`` with default frequency set to 100MHz, 0 degrees…
43 **Important note:** ``reg`` properties in ``clk0`` and ``clk1`` nodes reference the clock output n…
48 …ef:`Clock Control API <clock_control_api>` function ``clock_control_on()`` and a LiteX driver spec…
50 …tructure :c:struct:`litex_clk_setup` onto :c:type:`clock_control_subsys_t` and use it with :c:func…
51 | This code will try to set on ``clk0`` frequency 50MHz, 90 degrees of phase offset and 75% duty cy…
70 …ock output status (frequency, duty and phase offset) can be acquired with function ``clock_control…
82 * Setting frequency, duty and phase at once, then check clock status and rate,
91 Code is performed on 2 clock outputs with ``clkout_nr`` defined in ``LITEX_CLK_TEST_CLK1`` and ``LI…
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| /Zephyr-latest/soc/espressif/esp32c3/ |
| D | Kconfig | 26 ESP32-C3 revision v1.1 has updated ROM functions for Wi-Fi and BLE that
30 bool "Power down MAC and baseband of Wi-Fi and Bluetooth when PHY is disabled"
34 If enabled, the MAC and baseband of Wi-Fi and Bluetooth will be powered
|
| /Zephyr-latest/boards/raytac/mdbt53_db_40/doc/ |
| D | index.rst | 14 * a full-featured Arm Cortex-M33F core with DSP instructions, FPU, and
36 * RADIO (Bluetooth Low Energy and 802.15.4)
62 - Interfaces: SPI, UART, I2C, I2S, PWM, ADC, NFC, and USB
76 See `MDBT53-DB-40 website`_ and `MDBT53-DB-40 Specification`_
79 Connections and IOs
110 The IDAU is implemented with the System Protection Unit and is used to
111 define secure and non-secure memory maps. By default, all of the memory
112 space (Flash, SRAM, and peripheral address space) is defined to be secure
116 Programming and Debugging
125 to have Secure attribute set; the latter allows to build and run
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| /Zephyr-latest/boards/u-blox/ubx_bmd300eval/doc/ |
| D | index.rst | 3 u-blox EVK-BMD-30/35: BMD-300-EVAL, BMD-301-EVAL, and BMD-350-EVAL
9 The BMD-300-EVAL, BMD-301-EVAL, and BMD-350-EVAL hardware provides
10 support for the u-blox BMD-300, BMD-301, and BMD-350 Bluetooth 5
12 CPU and the following devices:
36 The BMD-300-EVAL, BMD-301-EVAL, and BMD-350-EVAL share the same
37 pin headers and assignments. The boards are different only in
38 the module used on the board. The BMD-300 and BMD-301 modules
39 share the same footprint and differ only in the antenna. The
42 More information about the BMD-300-EVAL, BMD-301-EVAL, and
43 BMD-350-EVAL and the respective modules can be found at the
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| /Zephyr-latest/boards/ti/cc1352r_sensortag/doc/ |
| D | index.rst | 15 The board is equipped with three LEDs, two push buttons and BoosterPack connectors
18 The CC13522 wireless MCU has a 48 MHz Arm |reg| Cortex |reg|-M4F SoC and an
19 integrated Sub-1 and 2.4 GHz transceiver supporting multiple protocols including
20 Bluetooth |reg| Low Energy and IEEE |reg| 802.15.4.
29 Connections and IOs
95 Programming and Debugging
98 TI's supported method of programming and debugging the ``CC1352R SensorTag`` is
100 (XDS110) debugger and serial console over USB.
105 #. Connect the 2-pin jumper cable to the top pins of RXD and TXD (grey wire to RXD, white wire to T…
106 #. Connect the other end of the 2-pin jumper to pins 12/RX and 13/TX on the LaunchPad SensorTag (Gr…
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| /Zephyr-latest/doc/connectivity/usb/device_next/ |
| D | usb_device.rst | 10 , :ref:`udc_api`, and USB device stack, :ref:`usbd_api`.
11 The :ref:`udc_api` provides a generic and vendor independent interface to USB
12 device controllers, and although, there a is clear separation between these
17 SoC has multiple controllers, they can be used simultaneously. Full and
21 classes and provides an API to implement custom USB functions.
23 The new USB device support is considered experimental and will replace
38 To build a sample that supports both the old and new USB device stack, set the
54 ``-DDEXTRA_CONF_FILE=overlay-usbd_next_ecm.conf`` and devicetree overlay file
57 How to configure and enable USB device support
61 common file for instantiation, configuration and initialization,
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| /Zephyr-latest/boards/nordic/nrf7002dk/doc/ |
| D | index.rst | 9 The nRF7002 DK (PCA10143) is a single-board development kit for evaluation and development on
12 Connectivity, Security, and Optimization categories. See `UG Wi-Fi certification`_ for detailed
16 layer and Medium Access Control (MAC) layer protocols. It implements the nRF Wi-Fi driver
22 * A full-featured Arm Cortex-M33F core with DSP instructions, FPU, and Armv8-M Security Extension,
40 contains the processor's information and the datasheet.
131 Connections and IOs
134 The connections and IOs supported by the development kit are listed in this section.
167 The IDAU is implemented with the System Protection Unit and is used to define
168 secure and non-secure memory maps. By default, the entire memory space
169 (Flash, SRAM, and peripheral address space) is defined to be secure-accessible only.
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| /Zephyr-latest/boards/nxp/imx95_evk/doc/ |
| D | index.rst | 18 - The processor integrates up to six Arm Cortex-A55 cores, and supports
19 functional safety with built-in Arm Cortex-M33 and -M7 cores
24 - USB interface: Two USB ports: Type-A and Type-C
27 - One audio codec WM8962BECSN/R with one TX and RX lane
46 - Supports XFI and USXGMII interfaces with one 10 Gbit RJ45 ICM connected
50 chip supporting 2x2 Wi-Fi 6 and Bluetooth 5.2
60 - FT4232H I2C interface: PCT2075 temperature sensor and current monitoring devices
100 The Zephyr ``imx95_evk/mimx9596/a55`` and ``imx95_evk/mimx9596/a55/smp`` board targets support
149 Programming and Debugging (A55)
152 Use this configuration to run basic Zephyr applications and kernel tests,
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| /Zephyr-latest/boards/silabs/radio_boards/slwrb4161a/doc/ |
| D | index.rst | 11 Mainboard BRD4001A and is supported as one of :ref:`silabs_radio_boards`.
21 - Operation frequency: 2.4 GHz and Sub-Ghz
22 - Crystals for LFXO (32.768 kHz) and HFXO (38.4 MHz).
24 For more information about the EFR32MG12 SoC and BRD4170A board, refer to these
37 Connections and IOs
41 means Pin number 2 on PORTA, as used in the board's datasheets and manuals.
78 The EFR32MG12P SoC has four USARTs and one Low Energy UARTs (LEUART).
79 USART0 is connected to the board controller and is used for the console.
81 Programming and Debugging
104 Reset the board and you should see the following message in the terminal:
|
| /Zephyr-latest/boards/silabs/radio_boards/slwrb4170a/doc/ |
| D | index.rst | 11 Mainboard BRD4001A and is supported as one of :ref:`silabs_radio_boards`.
21 - Operation frequency: 2.4 GHz and Sub-Ghz
22 - Crystals for LFXO (32.768 kHz) and HFXO (38.4 MHz).
24 For more information about the EFR32MG12 SoC and BRD4170A board, refer to these
37 Connections and IOs
41 means Pin number 2 on PORTA, as used in the board's datasheets and manuals.
78 The EFR32MG12P SoC has four USARTs and one Low Energy UARTs (LEUART).
79 USART0 is connected to the board controller and is used for the console.
81 Programming and Debugging
104 Reset the board and you should see the following message in the terminal:
|
| /Zephyr-latest/doc/services/portability/posix/overview/ |
| D | index.rst | 20 test, and diagnostic purposes.
23 application can be ported to run on the Zephyr kernel, and therefore leverage
24 Zephyr features and functionality. Additionally, a library designed to be
27 The POSIX API is an increasingly popular OSAL (operating system abstraction layer) for IoT and
28 embedded applications, as can be seen in Zephyr, AWS:FreeRTOS, TI-RTOS, and NuttX.
43 :ref:`Virtual Memory and MMUs <memory_management_api>`, Zephyr code and data normally share a
45 Zephyr kernel executable code and the application executable code are typically compiled into the
51 and experience limited user interaction. In such systems, full POSIX conformance can be
52 impractical and unnecessary.
72 via :ref:`Options<posix_options>` and :ref:`Option Groups<posix_option_groups>`.
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| /Zephyr-latest/boards/nxp/lpcxpresso55s28/doc/ |
| D | index.rst | 7 of and development with the LPC552x/S2x MCU based on the Arm® Cortex®-M33
9 subsystem and accelerometer, with several options for adding off-the-shelf
10 add-on boards for networking, sensors, displays, and other interfaces.
16 - 512 KB flash and 256 KB SRAM on-chip
17 - Onboard, high-speed USB, Link2 debug probe with CMSIS-DAP and SEGGER J-Link
19 - UART and SPI port bridging from LPC55S28 target to USB via the onboard debug
22 - 3 x user LEDs, plus Reset, ISP (3) and user buttons
26 - High and full speed USB ports with micro A/B connector for host or device
32 For more information about the LPC55S28 SoC and LPCXPresso55S28 board, see:
86 Connections and IOs
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| /Zephyr-latest/doc/connectivity/bluetooth/autopts/ |
| D | autopts-linux.rst | 7 virtual machine. Tested with Ubuntu 20.4 and Linux Mint 20.4.
33 https://www.nordicsemi.com/Software-and-tools/Development-Tools/nRF-Command-Line-Tools/Download.
46 and README.md. To install the tools, double click on each .deb file or follow
52 Choose and install your hypervisor like VMWare Workstation(preferred) or
55 Create Windows virtual machine instance. Make sure it has at least 2 cores and
58 Setup tested with VirtualBox 7.1.4 and VMWare Workstation 16.1.1 Pro.
70 It is possible to use NAT and portforwarding to setup communication between a Linux host and a
71 Windows guest. This is easiest setup for VirtualBox, and does not require any static IPs to be
72 configured, and will not get blocked by the Windows Firewall.
86 ``localhost:65000`` and ``localhost:65002`` (or ``127.0.0.0:65000`` and ``127.0.0.0:65002``)
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| /Zephyr-latest/doc/connectivity/bluetooth/ |
| D | bluetooth-ctlr-arch.rst | 19 * Vendor Specific, and Zephyr Driver usage
28 * States and roles, control procedures, packet controller
65 Upper Link Layer and Lower Link Layer
77 ULL and LLL Timing
150 * Interface with running procedures, local and remote
156 - rx_demux context to drive ull_cp_tx_ack() and ull_cp_rx()
157 * LLCP tx ack handling and PDU reception
161 Data structures and PDU helpers
166 * Defined in ull_conn_types.h and declared as part of struct ll_conn
167 * Holds local and remote procedure request queues as well as conn specific LLCP data
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| /Zephyr-latest/boards/nordic/nrf5340dk/doc/ |
| D | index.rst | 10 and development on the Nordic nRF5340 System-on-Chip (SoC).
14 * a full-featured Arm Cortex-M33F core with DSP instructions, FPU, and
35 * RADIO (Bluetooth Low Energy and 802.15.4)
52 contains the processor's information and the datasheet.
138 Connections and IOs
162 The IDAU is implemented with the System Protection Unit and is used to
163 define secure and non-secure memory maps. By default, all of the memory
164 space (Flash, SRAM, and peripheral address space) is defined to be secure
168 Programming and Debugging
177 to have Secure attribute set; the latter allows to build and run
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| /Zephyr-latest/boards/nxp/imx93_evk/doc/ |
| D | index.rst | 8 small and low cost package. The MCIMX93-EVK board is an entry-level development
12 i.MX93 MPU is composed of one cluster of 2x Cortex-A55 cores and a single
26 and 802.15.4
42 - MicroUSB for UART debug, two COM ports for A55 and M33
109 CPU's UART2 for A55 core and M33 core.
135 automatically selected if certain board function is enabled, and takes precedence
137 even if ``mux="B";`` is configured in dts, and an warning would be reported in
143 The user buttons RFU_BTN1 and RFU_BTN2 is connected to i.MX 93 GPIO by default,
157 Run the app, press RFU_BTN1 and the red LED turns on accordingly.
160 ``mimx9352/m33`` if I2C and PCAL6524 is enabled.
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| /Zephyr-latest/boards/shields/x_nucleo_iks02a1/doc/ |
| D | index.rst | 3 X-NUCLEO-IKS02A1: MEMS Inertial and Environmental Multi sensor shield
10 It is equipped with Arduino UNO R3 connector layout, and
11 is designed around the ISM330DHCX 3-axis accelerometer and 3-axis gyroscope,
12 the IIS2MDC 3-axis magnetometer, the IIS2DLPC 3-axis accelerometer and
16 and it is possible to change the default I2C port.
30 - ISM330DHCX MEMS 3D accelerometer (±2/±4/±8/±16 g) and
35 - DIL24 socket for additional MEMS adapters and other sensors (configurable in I2C or SPI)
47 - IIS2DLPC and ISM330DHCX are on I2C2
50 X-NUCLEO-IKS02A1 board can be configured in two different hardware modes, Mode 1 and Mode 2,
58 reside on the same I2C bus and are accessible from the main board mcu.
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| /Zephyr-latest/boards/renesas/ek_ra4l1/doc/ |
| D | index.rst | 8 and efficient platform-based product development.
20 **System Control and Ecosystem Access**
22 - USB Full Speed Host and Device (USB-C connector)
26 - External power supply (using surface mount clamp test points and power input vias)
32 - Debug out (SWD, SW0 and JTAG)
34 - User LEDs and buttons
46 - 2 Digilent PmodTM (SPI, UART and I2C) connectors
81 Programming and Debugging
85 built, flashed, and debugged in the usual way. See
86 :ref:`build_an_application` and :ref:`application_run` for more details on
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| /Zephyr-latest/boards/adi/max32650evkit/doc/ |
| D | index.rst | 24 - 120MHz High-Speed and 50MHz Low-Power Oscillators
26 - 32.768kHz and RTC Clock (Requires External Crystal)
30 - Five Low-Power Modes: Active, Sleep, Background, Deep-Sleep, and Backup
31 - 1.8V and 3.3V I/O with No Level Translators
32 - Programming and Debugging
54 - Trust Protection Unit (TPU) for IP/Data and Security
67 - Two General-Purpose LEDs and Two GeneralPurpose Pushbutton Switches
81 | CLOCK | on-chip | clock and reset control |
88 Programming and Debugging
106 appropriate adapter board and cable
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| /Zephyr-latest/boards/adi/max32650fthr/doc/ |
| D | index.rst | 24 - 120MHz High-Speed and 50MHz Low-Power Oscillators
26 - 32.768kHz and RTC Clock (Requires External Crystal)
30 - Five Low-Power Modes: Active, Sleep, Background, Deep-Sleep, and Backup
31 - 1.8V and 3.3V I/O with No Level Translators
32 - Programming and Debugging
54 - Trust Protection Unit (TPU) for IP/Data and Security
62 - Battery Connector and Charging Circuit
80 | CLOCK | on-chip | clock and reset control |
87 Programming and Debugging
105 appropriate adapter board and cable
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| /Zephyr-latest/boards/arm/v2m_musca_s1/doc/ |
| D | index.rst | 11 CPU and the following devices:
29 - ARM Cortex-M33 (with FPU and DSP)
65 - nSRST: Cortex-M33 system reset and CoreSight debug reset.
103 Musca-S1 is a Cortex-M33 based SoC and has 15 fixed exceptions and 77 IRQs.
108 Zephyr provides handlers for exceptions 1-7, 11, 12, 14, and 15, as listed
143 | | | | and IRQ offloading |
219 V2M Musca-S1 has a 32.768kHz crystal clock. The clock goes to a PLL and is
220 multiplied to drive the Cortex-M33 processors and SSE-200 subsystem. The
229 for RX/TX and no flow control (CTS/RTS) or FIFO. The Zephyr console output,
236 secure and non-secure memory maps. By default, all of the memory space is
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| /Zephyr-latest/doc/develop/api/ |
| D | api_lifecycle.rst | 8 maintaining and extending Zephyr's APIs need to be able to introduce
9 new APIs that aren't yet fully proven, and to potentially retire old APIs when they're
20 An up-to-date table of all APIs and their maturity level can be found in the
29 Experimental APIs denote that a feature was introduced recently, and may change
30 or be removed in future versions. Try it out and provide feedback
36 explaining its design and assumptions, how it is to be used, current
37 implementation limitations, and future potential, if appropriate.
42 When introducing a new and experimental API, mark the API version in the headers
50 peripheral or driver subsystem, review of the API is enforced and is driven by
62 testing to be considered stable. The API is considered generic in nature and can
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| /Zephyr-latest/doc/develop/flash_debug/ |
| D | nordic_segger.rst | 11 All Nordic nRF5x Development Kits, Preview Development Kits and Dongles are equipped
14 * Segger J-Link firmware and desktop tools
16 * Mass Storage device for drag-and-drop image flashing
24 To install the J-Link Software and documentation pack, follow the steps below:
26 #. Download the appropriate package from the `J-Link Software and documentation pack`_ website
35 including resetting it, erasing or programming the flash memory and more.
37 To install them, visit `nRF5x Command-Line Tools`_ and select your operating
49 to install the Segger J-Link Software and the nRF5x Command-Line Tools, follow the steps below:
51 * Connect the micro-USB cable to the nRF5x board and to your computer
67 and ``<x>`` is either 1 for nRF51-based boards or 2 for nRF52-based boards
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