tx (full) in projects: hal_espressif-latest

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Searched full:tx (Results 1 – 25 of 412) sorted by relevance

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/hal_espressif-latest/components/bt/esp_ble_mesh/mesh_core/
D	transport.c	57 #define SEG_RETRANSMIT_TIMEOUT_UNICAST(tx) (K_MSEC(400) + 50 * (tx)->ttl) argument 64 #define SEG_RETRANSMIT_TIMEOUT(tx) \ argument 65 (BLE_MESH_ADDR_IS_UNICAST((tx)->dst) ? \ 66 SEG_RETRANSMIT_TIMEOUT_UNICAST(tx) : \ 178 struct seg_tx tx = { in bt_mesh_get_seg_retrans_timeout() local 181 return SEG_RETRANSMIT_TIMEOUT_UNICAST(&tx); in bt_mesh_get_seg_retrans_timeout() 189 static int send_unseg(struct bt_mesh_net_tx tx, struct net_buf_simple sdu, in send_unseg() argument 195 tx->src, tx->ctx->addr, tx->ctx->app_idx, sdu->len); in send_unseg() 197 buf = bt_mesh_adv_create(BLE_MESH_ADV_DATA, tx->xmit, BUF_TIMEOUT); in send_unseg() 205 if (tx->ctx->app_idx == BLE_MESH_KEY_DEV) { in send_unseg() [all …]
D	adv.c	184 struct ble_adv_tx *tx = cb_data; in adv_send() local 186 if (tx == NULL) { in adv_send() 193 ADV_SCAN_INT(tx->param.interval), tx->param.duration, in adv_send() 194 tx->param.period, tx->param.count); in adv_send() 196 data.adv_data_len = tx->buf->data[0]; in adv_send() 198 memcpy(data.adv_data, tx->buf->data + 1, data.adv_data_len); in adv_send() 200 data.scan_rsp_data_len = tx->buf->data[data.adv_data_len + 1]; in adv_send() 202 … memcpy(data.scan_rsp_data, tx->buf->data + data.adv_data_len + 2, data.scan_rsp_data_len); in adv_send() 204 duration = tx->param.duration; in adv_send() 208 err = bt_mesh_ble_adv_start(&tx->param, &data); in adv_send() [all …]
/hal_espressif-latest/components/soc/esp32c3/include/soc/
D	i2s_struct.h	87 uint32_t tx_fifo_reset: 1; /Set this bit to reset Tx AFIFO/ 92 …right channel data in I2S TX mono mode or TDM channel select mode. 0: The invalid channel data is … 93 …uint32_t tx_big_endian: 1; /I2S Tx byte endian 1: low addr value to high addr. 0:… 94 …tx_update: 1; /Set 1 to update I2S TX registers from APB clock domain to I2S TX… 95 …e first channel data value is valid in I2S TX mono mode. 0: The second channel data value is val… 96 …uint32_t tx_pcm_conf: 2; /I2S TX compress/decompress configuration bit. & 0 (atol… 98 … /Set this bit to stop disable output BCK signal and WS signal when tx FIFO is emtpy/ 100 …uint32_t tx_left_align: 1; /1: I2S TX left alignment mode. 0: I2S TX right alignmen… 103 …uint32_t tx_bit_order: 1; /I2S Tx bit endian. 1:small endian the LSB is sent firs… 104 uint32_t tx_tdm_en: 1; /1: Enable I2S TDM Tx mode . 0: Disable.*/ [all …]
/hal_espressif-latest/components/soc/esp32s3/include/soc/
D	i2s_struct.h	89 uint32_t tx_fifo_reset : 1; /Set this bit to reset Tx AFIFO/ 94 …right channel data in I2S TX mono mode or TDM channel select mode. 0: The invalid channel data is … 95 …uint32_t tx_big_endian : 1; /I2S Tx byte endian, 1: low addr value to high ad… 96 …te : 1; /Set 1 to update I2S TX registers from APB clock domain to I2S TX… 97 …e first channel data value is valid in I2S TX mono mode. 0: The second channel data value is val… 98 …uint32_t tx_pcm_conf : 2; /I2S TX compress/decompress configuration bit. & … 100 … : 1; /Set this bit to stop disable output BCK signal and WS signal when tx FIFO is emtpy/ 102 …uint32_t tx_left_align : 1; /1: I2S TX left alignment mode. 0: I2S TX right a… 105 …uint32_t tx_bit_order : 1; /I2S Tx bit endian. 1:small endian, the LSB is se… 106 … uint32_t tx_tdm_en : 1; /1: Enable I2S TDM Tx mode . 0: Disable.*/ [all …]
D	gdma_struct.h	189 … : 1; /This bit is used to reset DMA channel 0 Tx FSM and Tx FIFO pointer./ 191 … /Set this bit to enable automatic outlink-writeback when all the data in tx buffer has been tran… 192 … 1; /EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 0 is generat… 193 … : 1; /Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading li… 194 … : 1; /Set this bit to 1 to enable INCR burst transfer for Tx channel 0 transmitti… 204 …uint32_t out_ext_mem_bk_size : 2; /Block size of Tx channel 0 when DMA access exter… 211 …last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 0./ 212 …when the last data pointed by one outlink descriptor has been read from memory for Tx channel 0. / 213 …r, including owner error, the second and third word error of outlink descriptor for Tx channel 0./ 214 …tlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 0.*/ [all …]
/hal_espressif-latest/components/soc/esp32c6/include/soc/
D	i2s_struct.h	262 * 0: UseI2S Tx module clock as I2S_MCLK_OUT. 1: UseI2S Rx module clock as 272 * I2S TX PCM2PDM configuration register 277 * I2S TX PDM bypass hp filter or not. The option has been removed. 281 * I2S TX PDM OSR2 value 285 * I2S TX PDM prescale for sigmadelta 289 * I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4 293 * I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4 297 * I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4 301 * I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4 305 * I2S TX PDM sigmadelta dither2 value [all …]
D	i2s_reg.h	277 * I2S TX configure register 288 * Set this bit to reset Tx AFIFO 317 * I2S TX mono mode or TDM channel select mode. 0: The invalid channel data is 318 * reg_i2s_single_data in I2S TX mono mode or TDM channel select mode. 325 * I2S Tx byte endian, 1: low addr value to high addr. 0: low addr with low addr 333 * Set 1 to update I2S TX registers from APB clock domain to I2S TX clock domain. This 341 * 1: The first channel data value is valid in I2S TX mono mode. 0: The second 342 * channel data value is valid in I2S TX mono mode. 349 * I2S TX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1 364 * Set this bit to stop disable output BCK signal and WS signal when tx FIFO is emtpy [all …]
/hal_espressif-latest/components/soc/esp32h2/include/soc/
D	i2s_struct.h	262 * 0: UseI2S Tx module clock as I2S_MCLK_OUT. 1: UseI2S Rx module clock as 272 * I2S TX PCM2PDM configuration register 277 * I2S TX PDM bypass hp filter or not. The option has been removed. 281 * I2S TX PDM OSR2 value 285 * I2S TX PDM prescale for sigmadelta 289 * I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4 293 * I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4 297 * I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4 301 * I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4 305 * I2S TX PDM sigmadelta dither2 value [all …]
D	i2s_reg.h	291 * I2S TX configure register 302 * Set this bit to reset Tx AFIFO 323 * Set this bit to stop disable output BCK signal and WS signal when tx FIFO is emtpy 331 * I2S TX mono mode or TDM channel select mode. 0: The invalid channel data is 332 * reg_i2s_single_data in I2S TX mono mode or TDM channel select mode. 346 * I2S Tx byte endian, 1: low addr value to high addr. 0: low addr with low addr 354 * Set 1 to update I2S TX registers from APB clock domain to I2S TX clock domain. This 362 * 1: The first channel data value is valid in I2S TX mono mode. 0: The second 363 * channel data value is valid in I2S TX mono mode. 370 * I2S TX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1 [all …]
/hal_espressif-latest/components/hal/esp32s3/include/hal/
D	i2s_ll.h	`71 * @brief Enable I2S tx module clock 91 * @brief Disable I2S tx module clock 111 * @brief I2S mclk use tx module clock 131 * @brief Enable I2S TX slave mode 153 * @brief Reset I2S TX module 175 * @brief Reset I2S TX FIFO 197 * @brief Set TX source clock 240 * @brief Set I2S tx bck div num 243 * @param val value to set tx bck div num 251 * @brief Set I2S tx raw clock division [all …]`
D	rmt_ll.h	8 …* @note TX and RX channels are index from 0 in the LL driver, i.e. tx_channel = [0,3], rx_channel … 146 ////////////////////////////////////////TX Channel Specific////////////////////////////////////////… 149 * @brief Reset clock divider for TX channels by mask 152 * @param channel_mask Mask of TX channels 161 * @brief Set TX channel clock divider 164 * @param channel RMT TX channel number 178 * @brief Reset RMT reading pointer for TX channel 181 * @param channel RMT TX channel number 193 * @brief Enable DMA access for TX channel 196 * @param channel RMT TX channel number [all …]
/hal_espressif-latest/components/hal/esp32c6/include/hal/
D	i2s_ll.h	`73 * @brief Enable I2S tx module clock 95 * @brief Disable I2S tx module clock 117 * @brief I2S mclk use tx module clock 139 * @brief Enable I2S TX slave mode 161 * @brief Reset I2S TX module 183 * @brief Reset I2S TX FIFO 205 * @brief Set TX source clock 251 * @brief Set I2S tx bck div num 254 * @param val value to set tx bck div num 262 * @brief Set I2S tx raw clock division [all …]`
D	rmt_ll.h	8 …* @note TX and RX channels are index from 0 in the LL driver, i.e. tx_channel = [0,1], rx_channel … 148 ////////////////////////////////////////TX Channel Specific////////////////////////////////////////… 151 * @brief Reset clock divider for TX channels by mask 154 * @param channel_mask Mask of TX channels 163 * @brief Set TX channel clock divider 166 * @param channel RMT TX channel number 180 * @brief Reset RMT reading pointer for TX channel 183 * @param channel RMT TX channel number 195 * @brief Start transmitting for TX channel 198 * @param channel RMT TX channel number [all …]
/hal_espressif-latest/components/hal/esp32c3/include/hal/
D	i2s_ll.h	`70 * @brief Enable I2S tx module clock 90 * @brief Disable I2S tx module clock 110 * @brief I2S mclk use tx module clock 130 * @brief Enable I2S TX slave mode 152 * @brief Reset I2S TX module 174 * @brief Reset I2S TX FIFO 196 * @brief Set TX source clock 240 * @brief Set I2S tx bck div num 243 * @param val value to set tx bck div num 251 * @brief Set I2S tx raw clock division [all …]`
D	rmt_ll.h	8 …* @note TX and RX channels are index from 0 in the LL driver, i.e. tx_channel = [0,1], rx_channel … 146 ////////////////////////////////////////TX Channel Specific////////////////////////////////////////… 149 * @brief Reset clock divider for TX channels by mask 152 * @param channel_mask Mask of TX channels 161 * @brief Set TX channel clock divider 164 * @param channel RMT TX channel number 178 * @brief Reset RMT reading pointer for TX channel 181 * @param channel RMT TX channel number 193 * @brief Start transmitting for TX channel 196 * @param channel RMT TX channel number [all …]
D	gdma_ll.h	267 ///////////////////////////////////// TX ///////////////////////////////////////// 269 * @brief Get DMA TX channel interrupt status word 278 * @brief Enable DMA TX channel interrupt 290 * @brief Clear DMA TX channel interrupt 299 * @brief Get DMA TX channel interrupt status register address 307 * @brief Enable DMA TX channel to check the owner bit in the descriptor, disabled by default 315 * @brief Enable DMA TX channel burst sending data, disabled by default 323 * @brief Enable DMA TX channel burst reading descriptor link, disabled by default 331 * @brief Set TX channel EOF mode 339 …* @brief Enable DMA TX channel automatic write results back to descriptor after all data has been … [all …]
/hal_espressif-latest/components/hal/esp32h2/include/hal/
D	i2s_ll.h	`74 * @brief Enable I2S tx module clock 96 * @brief Disable I2S tx module clock 118 * @brief I2S mclk use tx module clock 140 * @brief Enable I2S TX slave mode 162 * @brief Reset I2S TX module 184 * @brief Reset I2S TX FIFO 206 * @brief Set TX source clock 258 * @brief Set I2S tx bck div num 261 * @param val value to set tx bck div num 269 * @brief Set I2S tx raw clock division [all …]`
D	rmt_ll.h	8 …* @note TX and RX channels are index from 0 in the LL driver, i.e. tx_channel = [0,1], rx_channel … 145 ////////////////////////////////////////TX Channel Specific////////////////////////////////////////… 148 * @brief Reset clock divider for TX channels by mask 151 * @param channel_mask Mask of TX channels 160 * @brief Set TX channel clock divider 163 * @param channel RMT TX channel number 177 * @brief Reset RMT reading pointer for TX channel 180 * @param channel RMT TX channel number 192 * @brief Start transmitting for TX channel 195 * @param channel RMT TX channel number [all …]
/hal_espressif-latest/components/bt/include/esp32c3/include/
D	esp_bt.h	108 …* @brief Enable / disable the maximum TX/RX time limit for Coded-PHY connections in coexistence wi… 115 #define ESP_BT_HCI_TL_STATUS_OK (0) /!< HCI_TL Tx/Rx operation status OK / 414 …uint8_t ble_st_acl_tx_buf_nb; /!< Static ACL TX buffer numbers. Configurable in menucon… 431 uint8_t txant_dft; /!< Default TX antenna. Configurable in menuconfig. 437 …uint8_t txpwr_dft; /!< Default TX power. Please refer to `esp_power_level_t`… 453 …uint8_t coex_phy_coded_tx_rx_time_limit; /!< Enable / disable the maximum TX/RX time limit for C… 506 * @brief BLE TX power type 508 * This TX power type is used for the API `esp_ble_tx_power_set()` and `esp_ble_tx_power_get()`. 511 * 1. The connection TX power can only be set after the connection is established. 512 * After disconnecting, the corresponding TX power will not be affected. [all …]
/hal_espressif-latest/components/hal/esp32/include/hal/
D	i2s_ll.h	`120 * @brief I2S tx msb right enable 123 * @param enable Set true to enable tx msb right 142 * @brief I2S tx right channel first 164 * @brief I2S tx fifo module force enable 167 * @param enable Set true to enable tx fifo module 185 * @brief Enable I2S TX slave mode 207 * @brief Reset I2S TX module 233 * @brief Reset I2S TX FIFO 255 * @brief Set TX source clock 281 * @brief Set I2S tx bck div num [all …]`
/hal_espressif-latest/components/hal/esp32s2/include/hal/
D	i2s_ll.h	`118 * @brief I2S tx msb right enable 121 * @param enable Set true to enable tx msb right 140 * @brief I2S tx right channel first 162 * @brief I2S tx fifo module force enable 165 * @param enable Set true to enable tx fifo module 184 * @brief Enable I2S TX slave mode 206 * @brief Reset TX module 228 * @brief Reset TX FIFO 250 * @brief Set TX source clock 272 * @brief Set I2S tx bck div num [all …]`
D	rmt_ll.h	8 …* @note TX and RX channels are index from 0 in the LL driver, i.e. tx_channel = [0,3], rx_channel … 144 ////////////////////////////////////////TX Channel Specific////////////////////////////////////////… 147 * @brief Reset clock divider for TX channels by mask 150 * @param channel_mask Mask of TX channels 159 * @brief Set TX channel clock divider 162 * @param channel RMT TX channel number 176 * @brief Reset RMT reading pointer for TX channel 179 * @param channel RMT TX channel number 191 * @brief Start transmitting for TX channel 194 * @param channel RMT TX channel number [all …]
/hal_espressif-latest/components/hal/include/hal/
D	i2s_hal.h	62 …ata of the enabled channels will be sent, otherwise all data stored in DMA TX buffer will be sent … 68 /* PDM TX configurations / 79 …i2s_pdm_tx_line_mode_t line_mode; /!< PDM TX line mode, on-line codec, one-line dac, tw… 85 … } pdm_tx; /!< Specific configurations for PDM TX mode / 88 /* PDM TX configurations / 91 … } pdm_rx; /!< Specific configurations for PDM TX mode / 133 @brief Set tx channel clock 155 * @brief Set tx slot to standard mode 173 * @brief Enable tx channel as standard mode 193 * @brief Set tx slot to pdm mode [all …]
/hal_espressif-latest/components/esp_wifi/
D	Kconfig	44 prompt "Type of WiFi TX buffers" 47 Select type of WiFi TX buffers: 49 … If "Static" is selected, WiFi TX buffers are allocated when WiFi is initialized and released 50 when WiFi is de-initialized. The size of each static TX buffer is fixed to about 1.6KB. 52 … If "Dynamic" is selected, each WiFi TX buffer is allocated as needed when a data frame is 54 … has been sent by the WiFi driver. The size of each dynamic TX buffer depends on the length 57 If PSRAM is enabled, "Static" should be selected to guarantee enough WiFi TX buffers. 73 int "Max number of WiFi static TX buffers" 78 Set the number of WiFi static TX buffers. Each buffer takes approximately 1.6KB of RAM. 83 copy of it in a TX buffer. For some applications especially UDP applications, the upper [all …]
/hal_espressif-latest/components/hal/esp32c2/include/hal/
D	gdma_ll.h	267 ///////////////////////////////////// TX ///////////////////////////////////////// 269 * @brief Get DMA TX channel interrupt status word 278 * @brief Enable DMA TX channel interrupt 290 * @brief Clear DMA TX channel interrupt 299 * @brief Get DMA TX channel interrupt status register address 307 * @brief Enable DMA TX channel to check the owner bit in the descriptor, disabled by default 315 * @brief Enable DMA TX channel burst sending data, disabled by default 323 * @brief Enable DMA TX channel burst reading descriptor link, disabled by default 331 * @brief Set TX channel EOF mode 339 …* @brief Enable DMA TX channel automatic write results back to descriptor after all data has been … [all …]

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