Lines Matching full:tx
291 * I2S TX configure register
302 * Set this bit to reset Tx AFIFO
323 * Set this bit to stop disable output BCK signal and WS signal when tx FIFO is emtpy
331 * I2S TX mono mode or TDM channel select mode. 0: The invalid channel data is
332 * reg_i2s_single_data in I2S TX mono mode or TDM channel select mode.
346 * I2S Tx byte endian, 1: low addr value to high addr. 0: low addr with low addr
354 * Set 1 to update I2S TX registers from APB clock domain to I2S TX clock domain. This
362 * 1: The first channel data value is valid in I2S TX mono mode. 0: The second
363 * channel data value is valid in I2S TX mono mode.
370 * I2S TX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1
400 * 1: I2S TX left alignment mode. 0: I2S TX right alignment mode.
422 * I2S Tx bit endian. 1:small endian, the LSB is sent first. 0:big endian, the MSB is
430 * 1: Enable I2S TDM Tx mode . 0: Disable.
437 * 1: Enable I2S PDM Tx mode . 0: Disable.
504 * I2S TX configure register 1
526 * I2S Tx half sample bits -1.
533 * The Tx bit number for each channel minus 1in TDM mode.
566 * 0: UseI2S Tx module clock as I2S_MCLK_OUT. 1: UseI2S Rx module clock as
575 * I2S TX clock configure register
579 * Integral I2S TX clock divider value. f_I2S_CLK = f_I2S_CLK_S/(N+b/a). There will be
589 * I2S Tx module clock enable signal.
596 * Select I2S Tx module source clock. 0: XTAL clock. 1: APLL. 2: CLK160. 3:
649 * I2S TX module clock divider configure register
686 * I2S TX PCM2PDM configuration register
690 * I2S TX PDM bypass hp filter or not. The option has been removed.
697 * I2S TX PDM OSR2 value
704 * I2S TX PDM prescale for sigmadelta
711 * I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4
718 * I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4
725 * I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4
732 * I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4
739 * I2S TX PDM sigmadelta dither2 value
746 * I2S TX PDM sigmadelta dither value
753 * I2S TX PDM dac mode enable
760 * I2S TX PDM dac 2channel enable
767 * I2S TX PDM Converter enable
775 * I2S TX PCM2PDM configuration register
779 * I2S TX PDM Fp
786 * I2S TX PDM Fs
793 * The fourth parameter of PDM TX IIR_HP filter stage 2 is (504 +
801 * The fourth parameter of PDM TX IIR_HP filter stage 1 is (504 +
810 * I2S TX TDM mode control register
942 * The total channel number of I2S TX TDM mode.
950 * I2S TX TDM mode control register
954 * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output
962 * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output
970 * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output
978 * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output
986 * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output
994 * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output
1002 * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output
1010 * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output
1018 * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output
1026 * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output
1034 * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output
1042 * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output
1050 * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output
1058 * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output
1066 * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output
1074 * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output
1082 * The total channel number of I2S TX TDM mode.
1089 * When DMA TX buffer stores the data of (REG_TX_TDM_TOT_CHAN_NUM + 1) channels, and
1091 * it when all the data stored in DMA TX buffer is for enabled channels.
1144 * I2S TX timing control register
1148 * The delay mode of I2S TX SD output signal. 0: bypass. 1: delay by pos edge. 2:
1156 * The delay mode of I2S TX SD1 output signal. 0: bypass. 1: delay by pos edge. 2:
1164 * The delay mode of I2S TX WS output signal. 0: bypass. 1: delay by pos edge. 2:
1172 * The delay mode of I2S TX BCK output signal. 0: bypass. 1: delay by pos edge. 2:
1180 * The delay mode of I2S TX WS input signal. 0: bypass. 1: delay by pos edge. 2:
1188 * The delay mode of I2S TX BCK input signal. 0: bypass. 1: delay by pos edge. 2:
1250 * I2S TX status register