| /Zephyr-latest/dts/bindings/serial/ |
| D | uart-controller.yaml | 8 clock-frequency:
11 current-speed:
14 hw-flow-control:
23 - "none"
24 - "odd"
25 - "even"
26 stop-bits:
29 Sets the number of stop bits.
31 - "0_5"
32 - "1"
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| /Zephyr-latest/drivers/serial/ |
| D | uart_xlnx_ps.c | 1 /* uart_xlnx_ps.c - Xilinx Zynq family serial driver */
6 * SPDX-License-Identifier: Apache-2.0
19 * - the following macro for the number of bytes between register addresses:
41 /* For all register offsets and bits / bit masks:
42 * Comp. Xilinx Zynq-7000 Technical Reference Manual (ug585), chap. B.33
64 /* Control Register Bits Definition */
65 #define XUARTPS_CR_STOPBRK 0x00000100U /**< Stop transmission of break */
76 /* Mode Register Bits Definition */
84 #define XUARTPS_MR_STOPMODE_2_BIT 0x00000080U /**< 2 stop bits */
85 #define XUARTPS_MR_STOPMODE_1_5_BIT 0x00000040U /**< 1.5 stop bits */
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| D | uart_sy1xx.c | 2 * SPDX-License-Identifier: Apache-2.0
58 struct sy1xx_uart_config *config = (struct sy1xx_uart_config *)dev->config; in sy1xx_uart_configure()
60 if (uart_cfg->baudrate == 0) { in sy1xx_uart_configure()
61 return -1; in sy1xx_uart_configure()
66 * and then will restart from 0, so we must give div - 1 as in sy1xx_uart_configure()
69 uint32_t divider = sy1xx_soc_get_peripheral_clock() / uart_cfg->baudrate - 1; in sy1xx_uart_configure()
75 * [3]: stop bits 0 = 1 stop bit in sy1xx_uart_configure()
76 * 1 = 2 stop bits in sy1xx_uart_configure()
77 * [2:1]: bits 00 = 5 bits in sy1xx_uart_configure()
78 * 01 = 6 bits in sy1xx_uart_configure()
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| D | uart_efinix_sapphire.c | 4 * SPDX-License-Identifier: Apache-2.0
33 #define UART0_STOP 0 /* 1 stop bit */
57 return -1; in uart_efinix_sapphire_poll_in()
75 (uart_efinix_sapphire_cfg_0.baudrate * UART0_SAMPLE_PER_BAUD)) - in uart_efinix_sapphire_init()
80 /* 8 data bits, no parity, 1 stop bit */ in uart_efinix_sapphire_init()
81 uint32_t frame_config = (UART0_SAMPLE_PER_BAUD - 1) | UART0_PARITY << 8 | UART0_STOP << 16; in uart_efinix_sapphire_init()
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| D | uart_stm32.c | 2 * Copyright (c) 2016 Open-RnD Sp. z o.o.
6 * SPDX-License-Identifier: Apache-2.0
43 #include <zephyr/linker/linker-defs.h>
45 #include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
70 /* Placeholder value when wakeup-line DT property is not defined */
105 struct uart_stm32_data *data = dev->data; in uart_stm32_pm_policy_state_lock_get()
107 if (!data->pm_policy_state_on) { in uart_stm32_pm_policy_state_lock_get()
108 data->pm_policy_state_on = true; in uart_stm32_pm_policy_state_lock_get()
118 struct uart_stm32_data *data = dev->data; in uart_stm32_pm_policy_state_lock_put()
120 if (data->pm_policy_state_on) { in uart_stm32_pm_policy_state_lock_put()
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| /Zephyr-latest/samples/subsys/ipc/rpmsg_service/ |
| D | README.rst | 1 .. zephyr:code-sample:: rpmsg-service
3 :relevant-api: rpmsg_service_api
21 .. zephyr-app-commands::
22 :zephyr-app: samples/subsys/ipc/rpmsg_service
29 .. zephyr-app-commands::
30 :zephyr-app: samples/subsys/ipc/rpmsg_service
37 .. zephyr-app-commands::
38 :zephyr-app: samples/subsys/ipc/rpmsg_service
45 - Speed: 115200
46 - Data: 8 bits
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| /Zephyr-latest/drivers/i2c/ |
| D | i2c_dw.c | 1 /* dw_i2c.c - I2C file for Design Ware */
5 * Copyright (c) 2022 Andrei-Edward Popa
7 * SPDX-License-Identifier: Apache-2.0
49 #include "i2c-priv.h"
76 const struct i2c_dw_rom_config *const rom = dev->config; in cb_i2c_idma_transfer()
77 struct i2c_dw_dev_config *const dw = dev->data; in cb_i2c_idma_transfer()
79 dma_stop(rom->dma_dev, channel); in cb_i2c_idma_transfer()
83 dw->xfr_status = true; in cb_i2c_idma_transfer()
85 dw->xfr_status = false; in cb_i2c_idma_transfer()
94 write_rdlr(fifo_depth - 1, reg_base); in i2c_dw_set_fifo_th()
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| /Zephyr-latest/samples/subsys/ipc/ipc_service/icmsg/ |
| D | README.rst | 1 .. zephyr:code-sample:: ipc-icmsg
3 :relevant-api: ipc
17 .. zephyr-app-commands::
18 :zephyr-app: samples/subsys/ipc/ipc_service/icmsg
21 :west-args: --sysbuild
26 - Speed: 115200
27 - Data: 8 bits
28 - Parity: None
29 - Stop bits: 1
34 .. code-block:: console
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| /Zephyr-latest/drivers/dai/intel/ssp/ |
| D | dai-params-intel-ipc4.h | 4 * SPDX-License-Identifier: Apache-2.0
19 /**< HD/A host output (-> DSP). */
21 /**< HD/A host input (<- DSP). */
26 /**< HD/A link output (DSP ->). */
28 /**< HD/A link input (DSP <-). */
33 /**< DMIC link input (DSP <-). */
36 /**< I2S link output (DSP ->). */
38 /**< I2S link input (DSP <-). */
41 /**< ALH link output, legacy for SNDW (DSP ->). */
43 /**< ALH link input, legacy for SNDW (DSP <-). */
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| D | dai-params-intel-ipc3.h | 4 * SPDX-License-Identifier: Apache-2.0
38 * DAI_CONFIG flags. The 4 LSB bits are used for the commands, HW_PARAMS, HW_FREE and PAUSE
39 * representing when the IPC is sent. The 4 MSB bits are used to add quirks along with the above
53 * pipeline stop/pause and DAI DMA stop/pause should happen in two steps. This change is only
100 /* SSP Configuration Request - SOF_DAI_SSP_CONFIG */
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| /Zephyr-latest/samples/drivers/ipm/ipm_mcux/ |
| D | README.rst | 1 .. zephyr:code-sample:: ipm-mcux
3 :relevant-api: ipm_interface
5 Implement inter-processor mailbox (IPM) on NXP LPC family.
10 Some NXP microcontrollers from LPC family are dual-core, this
15 - :zephyr:board:`lpcxpresso54114`, two core processors (Cortex-M4F and Cortex-M0+)
16 - :zephyr:board:`lpcxpresso55s69`, two core processors (dual Cortex-M33)
21 - :zephyr:board:`lpcxpresso54114` board
22 - :zephyr:board:`lpcxpresso55s69` board
27 .. zephyr-app-commands::
28 :zephyr-app: samples/drivers/ipm/ipm_mcux
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| /Zephyr-latest/soc/mediatek/mt8xxx/ |
| D | mtk_adsp_load.py | 3 # SPDX-License-Identifier: Apache-2.0
27 # specific SOC anyway), so it really doesn't matter and we hard-code
30 # (For future reference: in /proc/device-tree on current ChromeOS
33 # that device node, and the two dram areas are "memory-region"
35 # nodes under "/reserved-memory").
46 compat = readfile(glob("/proc/device-tree/**/adsp@*/compatible", recursive=True)[0], "r")
47 m = re.match(r'.*(mt\d{4})-dsp', compat)
54 # also refers by reference to reserved-memory regions of system
60 path = glob("/proc/device-tree/**/adsp@*/", recursive=True)[0]
61 rnames = readfile(path + "reg-names", "r").split('\0')[:-1]
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| /Zephyr-latest/samples/boards/st/bluetooth/interactive_gui/ |
| D | README.rst | 1 .. _samples_boards_stm32_bluetooth_interactive-gui:
2 .. zephyr:code-sample:: st_bluetooth_interactive_gui
4 :relevant-api: bluenrg_hci_driver bluetooth
24 It depends on the board default settings for ``zephyr,bt-c2h-uart`` DTS property.
28 * 8 bits, no parity, 1 stop bit
37 https://www.st.com/en/embedded-software/stsw-bnrgui.html
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| /Zephyr-latest/drivers/i3c/ |
| D | i3c_mcux.c | 6 * SPDX-License-Identifier: Apache-2.0
24 * This is from NXP HAL which contains register bits macros
129 * @param reg Pointer to 32-bit Register.
135 * @retval -ETIMEDOUT Timedout without matching.
143 * quickly (some sub-microseconds) so no extra in reg32_poll_timeout()
147 return -ETIMEDOUT; in reg32_poll_timeout()
155 * @param reg Pointer to 32-bit Register.
173 * @param reg Pointer to 32-bit register.
177 * @return True if bits in @p mask mask matches @p match, false otherwise.
190 * @param reg Pointer to 32-bit register.
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| /Zephyr-latest/boards/gd/gd32a503v_eval/doc/ |
| D | index.rst | 6 The GD32A503V-EVAL board is a hardware platform that enables design and debug
7 of the GigaDevice A503 Cortex-M4F High Performance MCU.
9 The GD32A503VD features a single-core ARM Cortex-M4F MCU which can run up
10 to 120-MHz with flash accesses zero wait states, 384kiB of Flash, 48kiB of
16 - 2 user LEDs
17 - 2 user push buttons
18 - Reset Button
19 - ADC connected to a potentiometer
20 - 1 DAC channels
21 - GD25Q16 2Mib SPI Flash
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| /Zephyr-latest/samples/subsys/ipc/ipc_service/multi_endpoint/ |
| D | README.rst | 1 .. zephyr:code-sample:: ipc_multi_endpoint
2 :name: IPC service: Multi-endpoint
3 :relevant-api: ipc
14 .. zephyr-app-commands::
15 :zephyr-app: samples/subsys/ipc/ipc_service/multi_endpoint
22 * Data: 8 bits
24 * Stop bits: 1
29 .. code-block:: console
31 *** Booting Zephyr OS build v3.4.0-rc1-108-gccfbac8b0721 ***
32 IPC-service HOST [INST 0 - ENDP A] demo started
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| /Zephyr-latest/samples/drivers/mbox/ |
| D | README.rst | 1 .. zephyr:code-sample:: mbox
3 :relevant-api: mbox_interface
5 Perform inter-processor mailbox communication using the MBOX API.
20 .. zephyr-app-commands::
21 :zephyr-app: samples/drivers/mbox/
24 :west-args: --sysbuild
29 - Speed: 115200
30 - Data: 8 bits
31 - Parity: None
32 - Stop bits: 1
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| /Zephyr-latest/soc/sensry/ganymed/sy1xx/common/ |
| D | udma.h | 2 * SPDX-License-Identifier: Apache-2.0
45 * following bits
56 /* Stop and clear all pending transfers */
60 /* Configure for 8-bits transfer */
62 /* Configure for 16-bits transfer */
64 /* Configure for 32-bits transfer */
71 /* Clock-gating control register */
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| /Zephyr-latest/boards/gd/gd32e103v_eval/doc/ |
| D | index.rst | 6 The GD32E103V-EVAL board is a hardware platform that enables design and debug
7 of the GigaDevice E103 Cortex-M4F High Performance MCU.
9 The GD32E103VB features a single-core ARM Cortex-M4F MCU which can run up
10 to 120-MHz with flash accesses zero wait states, 128kiB of Flash, 32kiB of
16 - USB interface with mini-USB connector
17 - 4 user LEDs
18 - 4 user push buttons
19 - Reset Button
20 - ADC connected to a potentiometer
21 - 2 DAC channels
[all …]
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| /Zephyr-latest/samples/drivers/ipm/ipm_mhu_dual_core/ |
| D | README.rst | 1 .. zephyr:code-sample:: ipm-mhu-dual-core
3 :relevant-api: ipm_interface
5 Implement inter-processor mailbox (IPM) using an MHU (Message Handling Unit)
10 the processor cores. This sample is a simple dual-core example for a
23 -----------
28 .. zephyr-app-commands::
29 :zephyr-app: samples/drivers/ipm/ipm_mhu_dual_core
37 .. zephyr-app-commands::
38 :zephyr-app: samples/drivers/ipm/ipm_mhu_dual_core
46 A third-party tool (srecord) is used to generate the Intel formatted hex image.
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| /Zephyr-latest/include/zephyr/drivers/ |
| D | uart.h | 2 * Copyright (c) 2018-2019 Nordic Semiconductor ASA
5 * SPDX-License-Identifier: Apache-2.0
43 * @brief Reception stop reasons.
60 * start time + data bits + parity + stop bits.
69 * RS-485 half-duplex. This error is only valid on UARTs that
86 /** @brief Number of stop bits. */
88 UART_CFG_STOP_BITS_0_5, /**< 0.5 stop bit */
89 UART_CFG_STOP_BITS_1, /**< 1 stop bit */
90 UART_CFG_STOP_BITS_1_5, /**< 1.5 stop bits */
91 UART_CFG_STOP_BITS_2, /**< 2 stop bits */
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| /Zephyr-latest/samples/sensor/tmp116/ |
| D | README.rst | 29 * Breakout **GND** pin <--> Nucleo **GND** pin
30 * Breakout **VCC** pin <--> Nucleo **3V3** pin
31 * Breakout **SDA** pin <--> Nucleo **CN5-D14** pin
32 * Breakout **SCL** pin <--> Nucleo **CN5-D15** pin
40 .. zephyr-app-commands::
41 :zephyr-app: samples/sensor/tmp116
54 * Stop bits: 1
58 .. code-block:: console
60 Device TMP116 - 0x200010a8 is ready
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| /Zephyr-latest/boards/atmel/sam0/saml21_xpro/doc/ |
| D | index.rst | 7 prototyping with the SAM L21 Cortex®-M0+ processor-based
15 - SAML21J18 ARM Cortex-M0+ processor at 48 MHz
16 - 32.768 kHz crystal oscillator
17 - 256 KiB flash memory, 32 KiB of SRAM, 8KB Low Power SRAM
18 - One yellow user LED
19 - One mechanical user push button
20 - One reset button
21 - On-board USB based EDBG unit with serial console
29 .. list-table::
30 :header-rows: 1
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| /Zephyr-latest/boards/atmel/sam0/samc21n_xpro/doc/ |
| D | index.rst | 7 prototyping with the SAM C21N Cortex®-M0+ processor-based
15 - SAMC21N18A ARM Cortex-M0+ processor at 48 MHz
16 - 32.768 kHz crystal oscillator
17 - 256 KiB flash memory, 32 KiB of RAM, 8KB RRW flash
18 - One yellow user LED
19 - One mechanical user push button
20 - One reset button
21 - One QTouch® button
22 - On-board USB based EDBG unit with serial console
23 - Two CAN transceivers
[all …]
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| /Zephyr-latest/boards/atmel/sam0/samd21_xpro/doc/ |
| D | index.rst | 7 prototyping with the SAM D21 Cortex®-M0+ processor-based
15 - SAMD21J18 ARM Cortex-M0+ processor at 48 MHz
16 - 32.768 kHz crystal oscillator
17 - 256 KiB flash memory and 32 KiB of RAM
18 - One yellow user LED
19 - One mechanical user push button
20 - One reset button
21 - On-board USB based EDBG unit with serial console
29 .. list-table::
30 :header-rows: 1
[all …]
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