| /hal_espressif-latest/components/bt/esp_ble_mesh/mesh_core/ |
| D | transport.c | 662 static void update_rpl(struct bt_mesh_rpl *rpl, struct bt_mesh_net_rx *rx) in update_rpl() argument
664 rpl->src = rx->ctx.addr; in update_rpl()
665 rpl->seq = rx->seq; in update_rpl()
666 rpl->old_iv = rx->old_iv; in update_rpl()
678 bool bt_mesh_rpl_check(struct bt_mesh_net_rx *rx, struct bt_mesh_rpl **match) in bt_mesh_rpl_check() argument
683 if (rx->net_if == BLE_MESH_NET_IF_LOCAL) { in bt_mesh_rpl_check()
688 if (!rx->local_match) { in bt_mesh_rpl_check()
700 update_rpl(rpl, rx); in bt_mesh_rpl_check()
707 if (rpl->src == rx->ctx.addr) { in bt_mesh_rpl_check()
708 if (rx->old_iv && !rpl->old_iv) { in bt_mesh_rpl_check()
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| D | net.c | 110 static bool msg_cache_match(struct bt_mesh_net_rx *rx, in msg_cache_match() argument
125 static void msg_cache_add(struct bt_mesh_net_rx *rx) in msg_cache_add() argument
127 rx->msg_cache_idx = msg_cache_next++; in msg_cache_add()
128 msg_cache[rx->msg_cache_idx].src = rx->ctx.addr; in msg_cache_add()
129 msg_cache[rx->msg_cache_idx].seq = rx->seq; in msg_cache_add()
1071 size_t data_len, struct bt_mesh_net_rx *rx, in net_decrypt() argument
1077 rx->old_iv = (IVI(data) != (bt_mesh.iv_index & 0x01)); in net_decrypt()
1082 if (bt_mesh_net_obfuscate(buf->data, BLE_MESH_NET_IVI_RX(rx), priv)) { in net_decrypt()
1086 rx->ctx.addr = SRC(buf->data); in net_decrypt()
1087 if (!BLE_MESH_ADDR_IS_UNICAST(rx->ctx.addr)) { in net_decrypt()
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| D | prov.c | 91 #define XACT_SEG_DATA(_seg) (&link.rx.buf->data[20 + ((_seg - 1) * 23)])
92 #define XACT_SEG_RECV(_seg) (link.rx.seg &= ~(1 << (_seg)))
143 } rx; member
243 link.rx.prev_id = XACT_NVAL; in reset_state()
246 link.rx.buf = bt_mesh_proxy_server_get_buf(); in reset_state()
249 link.rx.buf = &rx_buf; in reset_state()
1347 static void link_open(struct prov_rx *rx, struct net_buf_simple *buf) in link_open() argument
1358 if (link.id == rx->link_id && link.expect == PROV_INVITE) { in link_open()
1377 link.id = rx->link_id; in link_open()
1379 net_buf_simple_reset(link.rx.buf); in link_open()
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| D | friend.h | 32 void bt_mesh_friend_enqueue_rx(struct bt_mesh_net_rx *rx,
48 int bt_mesh_friend_poll(struct bt_mesh_net_rx *rx, struct net_buf_simple *buf);
49 int bt_mesh_friend_req(struct bt_mesh_net_rx *rx, struct net_buf_simple *buf);
50 int bt_mesh_friend_clear(struct bt_mesh_net_rx *rx, struct net_buf_simple *buf);
51 int bt_mesh_friend_clear_cfm(struct bt_mesh_net_rx *rx,
53 int bt_mesh_friend_sub_add(struct bt_mesh_net_rx *rx,
55 int bt_mesh_friend_sub_rem(struct bt_mesh_net_rx *rx,
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| D | friend.c | 258 int bt_mesh_friend_clear(struct bt_mesh_net_rx *rx, struct net_buf_simple *buf) in bt_mesh_friend_clear() argument
264 .sub = rx->sub, in bt_mesh_friend_clear()
265 .ctx = &rx->ctx, in bt_mesh_friend_clear()
281 frnd = bt_mesh_friend_find(rx->sub->net_idx, lpn_addr, false, false); in bt_mesh_friend_clear()
633 int bt_mesh_friend_sub_add(struct bt_mesh_net_rx *rx, in bt_mesh_friend_sub_add() argument
644 frnd = bt_mesh_friend_find(rx->sub->net_idx, rx->ctx.addr, true, true); in bt_mesh_friend_sub_add()
646 BT_WARN("No matching LPN addr 0x%04x", rx->ctx.addr); in bt_mesh_friend_sub_add()
668 int bt_mesh_friend_sub_rem(struct bt_mesh_net_rx *rx, in bt_mesh_friend_sub_rem() argument
679 frnd = bt_mesh_friend_find(rx->sub->net_idx, rx->ctx.addr, true, true); in bt_mesh_friend_sub_rem()
681 BT_WARN("No matching LPN addr 0x%04x", rx->ctx.addr); in bt_mesh_friend_sub_rem()
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| /hal_espressif-latest/components/soc/esp32s3/include/soc/ |
| D | gdma_struct.h | 20 … : 1; /*This bit is used to reset DMA channel 0 Rx FSM and Rx FIFO pointer.*/
22 … : 1; /*Set this bit to 1 to enable INCR burst transfer for Rx channel 0 reading li…
23 … : 1; /*Set this bit to 1 to enable INCR burst transfer for Rx channel 0 receiving …
32 …s used to generate the INFIFO_FULL_WM_INT interrupt when Rx channel 0 received byte number in Rx F…
34 …uint32_t in_ext_mem_bk_size : 2; /*Block size of Rx channel 0 when DMA access exter…
41 …igh level when the last data pointed by one inlink descriptor has been received for Rx channel 0.*/
42 …Rx channel 0. For UHCI0, the raw interrupt bit turns to high level when the last data pointed by o…
43 …n data error is detected only in the case that the peripheral is UHCI0 for Rx channel 0. For other…
44 …or, including owner error, the second and third word error of inlink descriptor for Rx channel 0.*/
45 …rns to high level when Rx buffer pointed by inlink is full and receiving data is not completed, bu…
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| D | i2s_struct.h | 62 uint32_t rx_fifo_reset : 1; /*Set this bit to reset Rx AFIFO*/
68 …uint32_t rx_big_endian : 1; /*I2S Rx byte endian, 1: low addr value to high ad…
69 …te : 1; /*Set 1 to update I2S RX registers from APB clock domain to I2S RX…
70 …e first channel data value is valid in I2S RX mono mode. 0: The second channel data value is val…
71 …uint32_t rx_pcm_conf : 2; /*I2S RX compress/decompress configuration bit. & …
73 … I2S Rx only stop when reg_rx_start is cleared. 1: Stop when reg_rx_start is 0 or in_suc_eof is …
74 …uint32_t rx_left_align : 1; /*1: I2S RX left alignment mode. 0: I2S RX right a…
77 …uint32_t rx_bit_order : 1; /*I2S Rx bit endian. 1:small endian, the LSB is re…
78 … uint32_t rx_tdm_en : 1; /*1: Enable I2S TDM Rx mode . 0: Disable.*/
79 … uint32_t rx_pdm_en : 1; /*1: Enable I2S PDM Rx mode . 0: Disable.*/
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| /hal_espressif-latest/components/soc/esp32c3/include/soc/ |
| D | i2s_struct.h | 62 uint32_t rx_fifo_reset: 1; /*Set this bit to reset Rx AFIFO*/
68 …uint32_t rx_big_endian: 1; /*I2S Rx byte endian 1: low addr value to high addr. 0: …
69 …rx_update: 1; /*Set 1 to update I2S RX registers from APB clock domain to I2S RX…
70 …e first channel data value is valid in I2S RX mono mode. 0: The second channel data value is val…
71 …uint32_t rx_pcm_conf: 2; /*I2S RX compress/decompress configuration bit. & 0 (atol…
73 … I2S Rx only stop when reg_rx_start is cleared. 1: Stop when reg_rx_start is 0 or in_suc_eof is …
74 …uint32_t rx_left_align: 1; /*1: I2S RX left alignment mode. 0: I2S RX right alignmen…
77 …uint32_t rx_bit_order: 1; /*I2S Rx bit endian. 1:small endian the LSB is received …
78 uint32_t rx_tdm_en: 1; /*1: Enable I2S TDM Rx mode . 0: Disable.*/
79 uint32_t rx_pdm_en: 1; /*1: Enable I2S PDM Rx mode . 0: Disable.*/
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| D | gdma_struct.h | 18 …igh level when the last data pointed by one inlink descriptor has been received for Rx channel 0.*/
19 …Rx channel 0. For UHCI0 the raw interrupt bit turns to high level when the last data pointed by o…
20 …n data error is detected only in the case that the peripheral is UHCI0 for Rx channel 0. For other…
23 …or including owner error the second and third word error of inlink descriptor for Rx channel 0.*/
25 …rns to high level when Rx buffer pointed by inlink is full and receiving data is not completed bu…
27 …1; /*This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is overflo…
28 …1; /*This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is underfl…
130 … 1; /*This bit is used to reset DMA channel 0 Rx FSM and Rx FIFO pointer.*/
132 …: 1; /*Set this bit to 1 to enable INCR burst transfer for Rx channel 0 reading li…
133 …n: 1; /*Set this bit to 1 to enable INCR burst transfer for Rx channel 0 receiving …
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| /hal_espressif-latest/components/hal/include/hal/ |
| D | twai_hal.h | 155 * @brief Get the value of the RX Error Counter
158 * @return RX Error Counter Value
166 * @brief Get the RX message count register
169 * @return RX message count
227 /* ------------------------------- TX and RX -------------------------------- */
248 * This function takes a TWAI frame (in the format of the RX frame buffer) and
266 * self RX) in the command register.
274 * @brief Copy a frame from the RX buffer and release
276 * This function copies a frame from the RX buffer, then release the buffer (so
277 * that it loads the next frame in the RX FIFO). False is returned under the
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| /hal_espressif-latest/components/soc/esp32h2/include/soc/ |
| D | parl_io_struct.h | 13 /** Group: PARL_IO RX Mode Configuration */
15 * Parallel RX Sampling mode configuration register.
21 * Configures rx external enable signal selection from IO PAD.
58 /** Group: PARL_IO RX Data Configuration */
60 * Parallel RX data configuration register.
86 /** Group: PARL_IO RX General Configuration */
88 * Parallel RX general configuration register.
94 * Set this bit to enable the clock gating of output rx clock.
116 /** Group: PARL_IO RX Start Configuration */
118 * Parallel RX Start configuration register.
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| D | i2s_struct.h | 119 /** Group: RX Control and configuration registers */
121 * I2S RX configure register
130 * Set this bit to reset Rx AFIFO
142 * 0 : I2S Rx only stop when reg_rx_start is cleared. 1: Stop when reg_rx_start is
143 * 0 or in_suc_eof is 1. 2: Stop I2S RX when reg_rx_start is 0 or RX FIFO is full.
151 * I2S Rx byte endian, 1: low addr value to high addr. 0: low addr with low addr value.
155 * Set 1 to update I2S RX registers from APB clock domain to I2S RX clock domain. This
160 * 1: The first channel data value is valid in I2S RX mono mode. 0: The second
161 * channel data value is valid in I2S RX mono mode.
165 * I2S RX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1
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| /hal_espressif-latest/components/bootloader/subproject/components/micro-ecc/ |
| D | uECC_verify_antifault.c | 26 uECC_word_t rx[uECC_MAX_WORDS]; in uECC_verify_antifault() local
44 rx[num_n_words - 1] = 0; in uECC_verify_antifault()
97 uECC_vli_set(rx, point, num_words); in uECC_verify_antifault()
104 curve->double_jacobian(rx, ry, z, curve); in uECC_verify_antifault()
112 uECC_vli_modSub(tz, rx, tx, curve->p, num_words); /* Z = x2 - x1 */ in uECC_verify_antifault()
113 XYcZ_add(tx, ty, rx, ry, curve); in uECC_verify_antifault()
119 apply_z(rx, ry, z, curve); in uECC_verify_antifault()
122 if (uECC_vli_cmp(curve->n, rx, num_n_words) != 1) { in uECC_verify_antifault()
123 uECC_vli_sub(rx, rx, curve->n, num_n_words); in uECC_verify_antifault()
127 way that it will only happen if v == r (ie, rx == r) in uECC_verify_antifault()
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| /hal_espressif-latest/components/hal/esp32c2/include/hal/ |
| D | gdma_ll.h | 53 ///////////////////////////////////// RX /////////////////////////////////////////
55 * @brief Get DMA RX channel interrupt status word
64 * @brief Enable DMA RX channel interrupt
76 * @brief Clear DMA RX channel interrupt
85 * @brief Get DMA RX channel interrupt status register address
93 * @brief Enable DMA RX channel to check the owner bit in the descriptor, disabled by default
101 * @brief Enable DMA RX channel burst reading data, disabled by default
109 * @brief Enable DMA RX channel burst reading descriptor link, disabled by default
117 * @brief Reset DMA RX channel FSM and FIFO pointer
127 * @brief Check if DMA RX FIFO is full
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| /hal_espressif-latest/components/hal/esp32c3/include/hal/ |
| D | gdma_ll.h | 53 ///////////////////////////////////// RX /////////////////////////////////////////
55 * @brief Get DMA RX channel interrupt status word
64 * @brief Enable DMA RX channel interrupt
76 * @brief Clear DMA RX channel interrupt
85 * @brief Get DMA RX channel interrupt status register address
93 * @brief Enable DMA RX channel to check the owner bit in the descriptor, disabled by default
101 * @brief Enable DMA RX channel burst reading data, disabled by default
109 * @brief Enable DMA RX channel burst reading descriptor link, disabled by default
117 * @brief Reset DMA RX channel FSM and FIFO pointer
127 * @brief Check if DMA RX FIFO is full
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| /hal_espressif-latest/components/hal/esp32s3/include/hal/ |
| D | gdma_ll.h | 66 ///////////////////////////////////// RX /////////////////////////////////////////
68 * @brief Get DMA RX channel interrupt status word
77 * @brief Enable DMA RX channel interrupt
89 * @brief Clear DMA RX channel interrupt
98 * @brief Get DMA RX channel interrupt status register address
106 * @brief Enable DMA RX channel to check the owner bit in the descriptor, disabled by default
114 * @brief Enable DMA RX channel burst reading data, disabled by default
122 * @brief Enable DMA RX channel burst reading descriptor link, disabled by default
130 * @brief Reset DMA RX channel FSM and FIFO pointer
140 * @brief Set DMA RX channel memory block size
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| D | rmt_ll.h | 8 …* @note TX and RX channels are index from 0 in the LL driver, i.e. tx_channel = [0,3], rx_channel …
451 ////////////////////////////////////////RX Channel Specific////////////////////////////////////////…
454 * @brief Reset clock divider for RX channels by mask
457 * @param channel_mask Mask of RX channels
465 * @brief Set RX channel clock divider
468 * @param channel RMT RX channel number
482 * @brief Reset RMT writing pointer for RX channel
485 * @param channel RMT RX channel number
497 * @brief Enable DMA access for RX channel
500 * @param channel RMT RX channel number
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| /hal_espressif-latest/components/bt/porting/transport/driver/uart/ |
| D | hci_driver_uart_dma.c | 74 volatile bool is_continue_rx; /*!< Continue to rx */
80 #define ESP_BT_HCI_TL_STATUS_OK (0) /*!< HCI_TL Tx/Rx operation status OK */
83 /* Default block size for HCI RX data */
101 struct uart_txrxchannel rx; member
227 esp_bt_hci_tl_callback_t callback = uart_env.rx.callback; in hci_uart_tl_rx_eof_callback()
228 void *arg = uart_env.rx.arg; in hci_uart_tl_rx_eof_callback()
230 assert(uart_env.rx.callback != NULL); in hci_uart_tl_rx_eof_callback()
232 uart_env.rx.callback = NULL; in hci_uart_tl_rx_eof_callback()
233 uart_env.rx.arg = NULL; in hci_uart_tl_rx_eof_callback()
298 ESP_LOGE(TAG, "Will lost rx data, need adjust rxinfo memory count\n"); in hci_driver_uart_dma_recv_callback()
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| /hal_espressif-latest/components/esp_wifi/ |
| D | Kconfig | 9 int "Max number of WiFi static RX buffers"
15 Set the number of WiFi static RX buffers. Each buffer takes approximately 1.6KB of RAM.
16 The static rx buffers are allocated when esp_wifi_init is called, they are not freed
25 int "Max number of WiFi dynamic RX buffers"
30 … Set the number of WiFi dynamic RX buffers, 0 means unlimited RX buffers will be allocated
31 … (provided sufficient free RAM). The size of each dynamic RX buffer depends on the size of
34 … For each received data frame, the WiFi driver makes a copy to an RX buffer and then delivers
35 … it to the high layer TCP/IP stack. The dynamic RX buffer is freed after the higher layer has
39 … process them. In these cases we may run out of memory if RX buffer number is unlimited (0).
41 … If a dynamic RX buffer limit is set, it should be at least the number of static RX buffers.
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| /hal_espressif-latest/components/hal/esp32c6/include/hal/ |
| D | gdma_ll.h | 100 ///////////////////////////////////// RX /////////////////////////////////////////
102 * @brief Get DMA RX channel interrupt status word
111 * @brief Enable DMA RX channel interrupt
123 * @brief Clear DMA RX channel interrupt
132 * @brief Get DMA RX channel interrupt status register address
140 * @brief Enable DMA RX channel to check the owner bit in the descriptor, disabled by default
148 * @brief Enable DMA RX channel burst reading data, disabled by default
156 * @brief Enable DMA RX channel burst reading descriptor link, disabled by default
164 * @brief Reset DMA RX channel FSM and FIFO pointer
174 * @brief Check if DMA RX FIFO is full
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| /hal_espressif-latest/components/hal/esp32h2/include/hal/ |
| D | gdma_ll.h | 100 ///////////////////////////////////// RX /////////////////////////////////////////
102 * @brief Get DMA RX channel interrupt status word
111 * @brief Enable DMA RX channel interrupt
123 * @brief Clear DMA RX channel interrupt
132 * @brief Get DMA RX channel interrupt status register address
140 * @brief Enable DMA RX channel to check the owner bit in the descriptor, disabled by default
148 * @brief Enable DMA RX channel burst reading data, disabled by default
156 * @brief Enable DMA RX channel burst reading descriptor link, disabled by default
164 * @brief Reset DMA RX channel FSM and FIFO pointer
174 * @brief Check if DMA RX FIFO is full
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| /hal_espressif-latest/components/soc/esp32c6/include/soc/ |
| D | i2s_struct.h | 119 /** Group: RX Control and configuration registers */
121 * I2S RX configure register
130 * Set this bit to reset Rx AFIFO
148 * I2S Rx byte endian, 1: low addr value to high addr. 0: low addr with low addr value.
152 * Set 1 to update I2S RX registers from APB clock domain to I2S RX clock domain. This
157 * 1: The first channel data value is valid in I2S RX mono mode. 0: The second
158 * channel data value is valid in I2S RX mono mode.
162 * I2S RX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1
171 * 0 : I2S Rx only stop when reg_rx_start is cleared. 1: Stop when reg_rx_start is
172 * 0 or in_suc_eof is 1. 2: Stop I2S RX when reg_rx_start is 0 or RX FIFO is full.
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| D | gdma_struct.h | 21 * descriptor has been received for Rx channel 0.
26 * descriptor has been received for Rx channel 0. For UHCI0 the raw interrupt bit
28 * received and no data error is detected for Rx channel 0.
33 * case that the peripheral is UHCI0 for Rx channel 0. For other peripherals this raw
40 * Rx channel 0.
44 * The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full
45 * and receiving data is not completed but there is no more inlink for Rx channel 0.
49 * This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is
54 * This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is
369 * Configure 0 register of Rx channel 0
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| /hal_espressif-latest/components/hal/esp32s2/include/hal/ |
| D | i2s_ll.h | 129 * @brief I2S rx msb right enable
132 * @param enable Set true to enable rx msb right
151 * @brief I2S rx right channel first
173 * @brief I2S rx fifo module force enable
176 * @param enable Set true to enable rx fifo module
195 * @brief Enable I2S RX slave mode
217 * @brief Reset RX module
239 * @brief Reset RX FIFO
261 * @brief Set RX source clock
284 * @note mclk on ESP32S2 is shared by both TX and RX channel
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| /hal_espressif-latest/components/soc/esp32c2/include/soc/ |
| D | gdma_struct.h | 18 …igh level when the last data pointed by one inlink descriptor has been received for Rx channel 0.*/
19 …Rx channel 0. For UHCI0, the raw interrupt bit turns to high level when the last data pointed by o…
20 …n data error is detected only in the case that the peripheral is UHCI0 for Rx channel 0. For other…
23 …or, including owner error, the second and third word error of inlink descriptor for Rx channel 0.*/
25 …rns to high level when Rx buffer pointed by inlink is full and receiving data is not completed, bu…
27 …: 1; /*This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is overflo…
28 …: 1; /*This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is underfl…
138 … : 1; /*This bit is used to reset DMA channel 0 Rx FSM and Rx FIFO pointer.*/
140 … : 1; /*Set this bit to 1 to enable INCR burst transfer for Rx channel 0 reading li…
141 … : 1; /*Set this bit to 1 to enable INCR burst transfer for Rx channel 0 receiving …
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