Lines Matching full:rx

21          *  descriptor has been received for Rx channel 0.
26          *  descriptor has been received for Rx channel 0. For UHCI0 the raw interrupt bit
28          *  received and no data error is detected for Rx channel 0.
33          *  case that the peripheral is UHCI0 for Rx channel 0. For other peripherals this raw
40          *  Rx channel 0.
44          *  The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full
45          *  and receiving data is not completed but there is no more inlink for Rx channel 0.
49          *  This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is
54          *  This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is
369  *  Configure 0 register of Rx channel 0
374          *  This bit is used to reset DMA channel 0 Rx FSM and Rx FIFO pointer.
382          *  Set this bit to 1 to enable INCR burst transfer for Rx channel 0 reading link
387          *  Set this bit to 1 to enable INCR burst transfer for Rx channel 0 receiving data
396          *  Set this bit to 1 to enable etm control mode, dma Rx channel 0 is triggered by etm
406  *  Configure 1 register of Rx channel 0
421  *  Pop control register of Rx channel 0
439  *  Link descriptor configure and control register of Rx channel 0
534  *  Push control register of Rx channel 0
600  *  Receive FIFO status of Rx channel 0
605          *  L1 Rx FIFO full signal for Rx channel 0.
609          *  L1 Rx FIFO empty signal for Rx channel 0.
613          *  The register stores the byte number of the data in L1 Rx FIFO for Rx channel 0.
643  *  Receive status of Rx channel 0
665  *  Inlink descriptor address when EOF occurs of Rx channel 0
679  *  Inlink descriptor address when errors occur of Rx channel 0
693  *  Current inlink descriptor address of Rx channel 0
706  *  The last inlink descriptor address of Rx channel 0
719  *  The second-to-last inlink descriptor address of Rx channel 0
862  *  Priority register of Rx channel 0
867          *  The priority of Rx channel 0. The larger of the value the higher of the priority.
892  *  Peripheral selection of Rx channel 0
897          *  This register is used to select peripheral for Rx channel 0. 0:SPI2. 1: reserved.