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/Zephyr-Core-3.7.0/include/zephyr/devicetree/
Dreset.h27 * "resets" phandle-array property at an index
36 * resets = <&reset1 10>, <&reset2 20>;
45 * @param idx logical index into "resets"
51 DT_PHANDLE_BY_IDX(node_id, resets, idx)
57 * in "resets"
65 * resets phandle-array property by name
74 * resets = <&reset1 10>, <&reset2 20>;
84 * @param name lowercase-and-underscores name of a resets element
90 DT_PHANDLE_BY_NAME(node_id, resets, name)
103 * resets = <&reset 10>;
[all …]
/Zephyr-Core-3.7.0/dts/arm/gd/gd32f4xx/
Dgd32f4xx.dtsi76 resets = <&rctl GD32_RESET_USART0>;
85 resets = <&rctl GD32_RESET_USART1>;
94 resets = <&rctl GD32_RESET_USART2>;
103 resets = <&rctl GD32_RESET_UART3>;
112 resets = <&rctl GD32_RESET_UART4>;
121 resets = <&rctl GD32_RESET_USART5>;
130 resets = <&rctl GD32_RESET_UART6>;
139 resets = <&rctl GD32_RESET_UART7>;
147 resets = <&rctl GD32_RESET_DAC>;
162 resets = <&rctl GD32_RESET_I2C0>;
[all …]
Dgd32f450.dtsi17 resets = <&rctl GD32_RESET_SPI3>;
28 resets = <&rctl GD32_RESET_SPI4>;
39 resets = <&rctl GD32_RESET_SPI5>;
/Zephyr-Core-3.7.0/dts/arm/gd/gd32f403/
Dgd32f403.dtsi78 resets = <&rctl GD32_RESET_USART0>;
87 resets = <&rctl GD32_RESET_USART1>;
96 resets = <&rctl GD32_RESET_USART2>;
105 resets = <&rctl GD32_RESET_UART3>;
114 resets = <&rctl GD32_RESET_UART4>;
123 resets = <&rctl GD32_RESET_SPI0>;
134 resets = <&rctl GD32_RESET_SPI1>;
145 resets = <&rctl GD32_RESET_SPI2>;
156 resets = <&rctl GD32_RESET_ADC0>;
167 resets = <&rctl GD32_RESET_ADC1>;
[all …]
/Zephyr-Core-3.7.0/dts/arm/gd/gd32e10x/
Dgd32e10x.dtsi71 resets = <&rctl GD32_RESET_USART0>;
80 resets = <&rctl GD32_RESET_USART1>;
89 resets = <&rctl GD32_RESET_USART2>;
98 resets = <&rctl GD32_RESET_UART3>;
107 resets = <&rctl GD32_RESET_UART4>;
115 resets = <&rctl GD32_RESET_DAC>;
130 resets = <&rctl GD32_RESET_I2C0>;
143 resets = <&rctl GD32_RESET_I2C1>;
177 resets = <&rctl GD32_RESET_WWDGT>;
195 resets = <&rctl GD32_RESET_GPIOA>;
[all …]
/Zephyr-Core-3.7.0/dts/arm/nuvoton/
Dm46x.dtsi90 resets = <&rst NUMAKER_UART0_RST>;
100 resets = <&rst NUMAKER_UART1_RST>;
110 resets = <&rst NUMAKER_UART2_RST>;
120 resets = <&rst NUMAKER_UART3_RST>;
130 resets = <&rst NUMAKER_UART4_RST>;
140 resets = <&rst NUMAKER_UART5_RST>;
150 resets = <&rst NUMAKER_UART6_RST>;
160 resets = <&rst NUMAKER_UART7_RST>;
170 resets = <&rst NUMAKER_UART8_RST>;
180 resets = <&rst NUMAKER_UART9_RST>;
[all …]
Dm2l31x.dtsi81 resets = <&rst NUMAKER_UART0_RST>;
91 resets = <&rst NUMAKER_UART1_RST>;
101 resets = <&rst NUMAKER_UART2_RST>;
111 resets = <&rst NUMAKER_UART3_RST>;
121 resets = <&rst NUMAKER_UART4_RST>;
131 resets = <&rst NUMAKER_UART5_RST>;
141 resets = <&rst NUMAKER_UART6_RST>;
151 resets = <&rst NUMAKER_UART7_RST>;
228 resets = <&rst NUMAKER_SPI0_RST>;
239 resets = <&rst NUMAKER_SPI1_RST>;
[all …]
/Zephyr-Core-3.7.0/dts/arm/gd/gd32e50x/
Dgd32e50x.dtsi84 resets = <&rctl GD32_RESET_USART0>;
93 resets = <&rctl GD32_RESET_USART1>;
102 resets = <&rctl GD32_RESET_USART2>;
111 resets = <&rctl GD32_RESET_UART3>;
120 resets = <&rctl GD32_RESET_UART4>;
130 resets = <&rctl GD32_RESET_USART5>;
138 resets = <&rctl GD32_RESET_DAC>;
153 resets = <&rctl GD32_RESET_I2C0>;
166 resets = <&rctl GD32_RESET_I2C1>;
179 resets = <&rctl GD32_RESET_I2C2>;
[all …]
Dgd32e507xe.dtsi18 resets = <&rctl GD32_RESET_TIMER7>;
36 resets = <&rctl GD32_RESET_TIMER8>;
53 resets = <&rctl GD32_RESET_TIMER9>;
70 resets = <&rctl GD32_RESET_TIMER10>;
87 resets = <&rctl GD32_RESET_TIMER11>;
104 resets = <&rctl GD32_RESET_TIMER12>;
121 resets = <&rctl GD32_RESET_TIMER13>;
/Zephyr-Core-3.7.0/dts/arm/gd/gd32a50x/
Dgd32a50x.dtsi79 resets = <&rctl GD32_RESET_USART0>;
88 resets = <&rctl GD32_RESET_USART1>;
97 resets = <&rctl GD32_RESET_USART2>;
105 resets = <&rctl GD32_RESET_DAC>;
120 resets = <&rctl GD32_RESET_I2C0>;
133 resets = <&rctl GD32_RESET_I2C1>;
142 resets = <&rctl GD32_RESET_SPI0>;
153 resets = <&rctl GD32_RESET_SPI1>;
164 resets = <&rctl GD32_RESET_ADC0>;
175 resets = <&rctl GD32_RESET_ADC1>;
[all …]
/Zephyr-Core-3.7.0/dts/riscv/gd/
Dgd32vf103.dtsi98 resets = <&rctl GD32_RESET_USART0>;
107 resets = <&rctl GD32_RESET_USART1>;
116 resets = <&rctl GD32_RESET_USART2>;
125 resets = <&rctl GD32_RESET_UART3>;
134 resets = <&rctl GD32_RESET_UART4>;
143 resets = <&rctl GD32_RESET_ADC0>;
154 resets = <&rctl GD32_RESET_ADC1>;
164 resets = <&rctl GD32_RESET_DAC>;
179 resets = <&rctl GD32_RESET_I2C0>;
188 resets = <&rctl GD32_RESET_SPI0>;
[all …]
/Zephyr-Core-3.7.0/dts/arm64/intel/
Dintel_socfpga_agilex5.dtsi112 resets = <&reset RSTMGR_UART0_RSTLINE>;
131 resets = <&reset RSTMGR_SDMMC_RSTLINE>,
144 resets = <&reset RSTMGR_SPTIMER0_RSTLINE>;
155 resets = <&reset RSTMGR_SPTIMER1_RSTLINE>;
166 resets = <&reset RSTMGR_L4SYSTIMER0_RSTLINE>;
177 resets = <&reset RSTMGR_L4SYSTIMER1_RSTLINE>;
184 resets = <&reset RSTMGR_WATCHDOG0_RSTLINE>;
192 resets = <&reset RSTMGR_WATCHDOG1_RSTLINE>;
200 resets = <&reset RSTMGR_WATCHDOG2_RSTLINE>;
208 resets = <&reset RSTMGR_WATCHDOG3_RSTLINE>;
[all …]
/Zephyr-Core-3.7.0/dts/arm/st/f4/
Dstm32f413.dtsi17 resets = <&rctl STM32_RESET(APB1, 19U)>;
26 resets = <&rctl STM32_RESET(APB1, 20U)>;
35 resets = <&rctl STM32_RESET(APB1, 30U)>;
44 resets = <&rctl STM32_RESET(APB1, 31U)>;
53 resets = <&rctl STM32_RESET(APB2, 6U)>;
62 resets = <&rctl STM32_RESET(APB2, 7U)>;
/Zephyr-Core-3.7.0/dts/arm/gd/gd32l23x/
Dgd32l23x.dtsi74 resets = <&rctl GD32_RESET_USART0>;
83 resets = <&rctl GD32_RESET_USART1>;
92 resets = <&rctl GD32_RESET_UART3>;
101 resets = <&rctl GD32_RESET_ADC>;
133 resets = <&rctl GD32_RESET_GPIOA>;
143 resets = <&rctl GD32_RESET_GPIOB>;
153 resets = <&rctl GD32_RESET_GPIOC>;
163 resets = <&rctl GD32_RESET_GPIOD>;
173 resets = <&rctl GD32_RESET_GPIOF>;
/Zephyr-Core-3.7.0/dts/arm/gd/gd32f3x0/
Dgd32f3x0.dtsi70 resets = <&rctl GD32_RESET_USART0>;
79 resets = <&rctl GD32_RESET_USART1>;
89 resets = <&rctl GD32_RESET_ADC>;
115 resets = <&rctl GD32_RESET_WWDGT>;
133 resets = <&rctl GD32_RESET_GPIOA>;
143 resets = <&rctl GD32_RESET_GPIOB>;
153 resets = <&rctl GD32_RESET_GPIOC>;
163 resets = <&rctl GD32_RESET_GPIOD>;
173 resets = <&rctl GD32_RESET_GPIOF>;
/Zephyr-Core-3.7.0/dts/arm/st/f0/
Dstm32f030Xc.dtsi33 resets = <&rctl STM32_RESET(APB1, 18U)>;
42 resets = <&rctl STM32_RESET(APB1, 19U)>;
51 resets = <&rctl STM32_RESET(APB1, 20U)>;
60 resets = <&rctl STM32_RESET(APB2, 5U)>;
69 resets = <&rctl STM32_RESET(APB1, 5U)>;
Dstm32f091.dtsi23 resets = <&rctl STM32_RESET(APB1, 20U)>;
32 resets = <&rctl STM32_RESET(APB2, 5U)>;
41 resets = <&rctl STM32_RESET(APB2, 6U)>;
50 resets = <&rctl STM32_RESET(APB2, 7U)>;
/Zephyr-Core-3.7.0/dts/arm/st/h5/
Dstm32h562.dtsi115 resets = <&rctl STM32_RESET(APB1L, 19U)>;
124 resets = <&rctl STM32_RESET(APB1L, 20U)>;
133 resets = <&rctl STM32_RESET(APB1L, 30U)>;
142 resets = <&rctl STM32_RESET(APB1L, 31U)>;
151 resets = <&rctl STM32_RESET(APB1H, 0U)>;
160 resets = <&rctl STM32_RESET(APB1L, 25U)>;
169 resets = <&rctl STM32_RESET(APB1L, 26U)>;
178 resets = <&rctl STM32_RESET(APB1L, 27U)>;
187 resets = <&rctl STM32_RESET(APB1H, 1U)>;
278 resets = <&rctl STM32_RESET(APB1L, 2U)>;
[all …]
/Zephyr-Core-3.7.0/dts/arm/nxp/
Dnxp_lpc51u68.dtsi101 resets = <&reset NXP_SYSCON_RESET(1, 11)>;
110 resets = <&reset NXP_SYSCON_RESET(1, 12)>;
119 resets = <&reset NXP_SYSCON_RESET(1, 13)>;
128 resets = <&reset NXP_SYSCON_RESET(1, 14)>;
137 resets = <&reset NXP_SYSCON_RESET(1, 15)>;
146 resets = <&reset NXP_SYSCON_RESET(1, 16)>;
155 resets = <&reset NXP_SYSCON_RESET(1, 17)>;
164 resets = <&reset NXP_SYSCON_RESET(1, 18)>;
Dnxp_lpc55S0x_common.dtsi159 resets = <&reset NXP_SYSCON_RESET(1, 11)>;
168 resets = <&reset NXP_SYSCON_RESET(1, 12)>;
177 resets = <&reset NXP_SYSCON_RESET(1, 13)>;
186 resets = <&reset NXP_SYSCON_RESET(1, 14)>;
195 resets = <&reset NXP_SYSCON_RESET(1, 15)>;
204 resets = <&reset NXP_SYSCON_RESET(1, 16)>;
213 resets = <&reset NXP_SYSCON_RESET(1, 17)>;
222 resets = <&reset NXP_SYSCON_RESET(1, 18)>;
231 resets = <&reset NXP_SYSCON_RESET(2, 28)>;
243 resets = <&reset NXP_SYSCON_RESET(1, 7)>;
/Zephyr-Core-3.7.0/dts/arm/st/f1/
Dstm32f103Xg.dtsi36 resets = <&rctl STM32_RESET(APB2, 19U)>;
53 resets = <&rctl STM32_RESET(APB2, 20U)>;
70 resets = <&rctl STM32_RESET(APB2, 21U)>;
87 resets = <&rctl STM32_RESET(APB1, 6U)>;
104 resets = <&rctl STM32_RESET(APB1, 7U)>;
121 resets = <&rctl STM32_RESET(APB1, 8U)>;
/Zephyr-Core-3.7.0/dts/arm/st/l0/
Dstm32l071.dtsi61 resets = <&rctl STM32_RESET(APB1, 1U)>;
83 resets = <&rctl STM32_RESET(APB1, 4U)>;
99 resets = <&rctl STM32_RESET(APB1, 5U)>;
115 resets = <&rctl STM32_RESET(APB2, 5U)>;
137 resets = <&rctl STM32_RESET(APB2, 14U)>;
146 resets = <&rctl STM32_RESET(APB1, 19U)>;
155 resets = <&rctl STM32_RESET(APB1, 20U)>;
/Zephyr-Core-3.7.0/dts/arm/st/l4/
Dstm32l471.dtsi52 resets = <&rctl STM32_RESET(APB1L, 18U)>;
61 resets = <&rctl STM32_RESET(APB1L, 19U)>;
70 resets = <&rctl STM32_RESET(APB1L, 20U)>;
111 resets = <&rctl STM32_RESET(APB1L, 1U)>;
133 resets = <&rctl STM32_RESET(APB1L, 2U)>;
155 resets = <&rctl STM32_RESET(APB1L, 3U)>;
177 resets = <&rctl STM32_RESET(APB1L, 5U)>;
193 resets = <&rctl STM32_RESET(APB2, 13U)>;
210 resets = <&rctl STM32_RESET(APB2, 18U)>;
242 resets = <&rctl STM32_RESET(APB2, 10U)>;
/Zephyr-Core-3.7.0/dts/arm/st/g0/
Dstm32g070.dtsi18 resets = <&rctl STM32_RESET(APB1L, 18U)>;
27 resets = <&rctl STM32_RESET(APB1L, 19U)>;
36 resets = <&rctl STM32_RESET(APB1H, 16U)>;
/Zephyr-Core-3.7.0/dts/arm/rpi_pico/
Drp2040.dtsi246 resets = <&reset RPI_PICO_RESETS_RESET_UART0>;
256 resets = <&reset RPI_PICO_RESETS_RESET_UART1>;
268 resets = <&reset RPI_PICO_RESETS_RESET_SPI0>;
279 resets = <&reset RPI_PICO_RESETS_RESET_SPI1>;
289 resets = <&reset RPI_PICO_RESETS_RESET_ADC>;
302 resets = <&reset RPI_PICO_RESETS_RESET_I2C0>;
314 resets = <&reset RPI_PICO_RESETS_RESET_I2C1>;
331 resets = <&reset RPI_PICO_RESETS_RESET_USBCTRL>;
342 resets = <&reset RPI_PICO_RESETS_RESET_PWM>;
353 resets = <&reset RPI_PICO_RESETS_RESET_TIMER>;
[all …]

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