Lines Matching full:resets
84 resets = <&rctl GD32_RESET_USART0>;
93 resets = <&rctl GD32_RESET_USART1>;
102 resets = <&rctl GD32_RESET_USART2>;
111 resets = <&rctl GD32_RESET_UART3>;
120 resets = <&rctl GD32_RESET_UART4>;
130 resets = <&rctl GD32_RESET_USART5>;
138 resets = <&rctl GD32_RESET_DAC>;
153 resets = <&rctl GD32_RESET_I2C0>;
166 resets = <&rctl GD32_RESET_I2C1>;
179 resets = <&rctl GD32_RESET_I2C2>;
213 resets = <&rctl GD32_RESET_WWDGT>;
231 resets = <&rctl GD32_RESET_GPIOA>;
241 resets = <&rctl GD32_RESET_GPIOB>;
251 resets = <&rctl GD32_RESET_GPIOC>;
261 resets = <&rctl GD32_RESET_GPIOD>;
271 resets = <&rctl GD32_RESET_GPIOE>;
281 resets = <&rctl GD32_RESET_GPIOF>;
291 resets = <&rctl GD32_RESET_GPIOG>;
302 resets = <&rctl GD32_RESET_TIMER0>;
320 resets = <&rctl GD32_RESET_TIMER1>;
338 resets = <&rctl GD32_RESET_TIMER2>;
355 resets = <&rctl GD32_RESET_TIMER3>;
372 resets = <&rctl GD32_RESET_TIMER4>;
390 resets = <&rctl GD32_RESET_TIMER5>;
401 resets = <&rctl GD32_RESET_TIMER6>;