1/* 2 * SPDX-License-Identifier: Apache-2.0 3 * 4 * Copyright (C) 2023, Intel Corporation 5 * 6 */ 7 8#include <arm64/armv8-a.dtsi> 9#include <zephyr/dt-bindings/interrupt-controller/arm-gic.h> 10#include <zephyr/dt-bindings/reset/intel_socfpga_reset.h> 11#include <mem.h> 12 13/ { 14 cpus { 15 #address-cells = <1>; 16 #size-cells= <0>; 17 18 cpu@0 { 19 device_type = "cpu"; 20 compatible = "arm,cortex-a55"; 21 enable-method = "psci"; 22 reg = <0x0>; 23 }; 24 25 cpu@100 { 26 device_type = "cpu"; 27 compatible = "arm,cortex-a55"; 28 enable-method = "psci"; 29 reg = <0x100>; 30 }; 31 32 cpu@200 { 33 device_type = "cpu"; 34 compatible = "arm,cortex-a76"; 35 enable-method = "psci"; 36 reg = <0x200>; 37 }; 38 39 cpu@300 { 40 device_type = "cpu"; 41 compatible = "arm,cortex-a76"; 42 enable-method = "psci"; 43 reg = <0x300>; 44 }; 45 }; 46 47 gic: interrupt-controller@1d000000 { 48 compatible = "arm,gic-v3", "arm,gic"; 49 reg = <0x1d000000 0x10000>, /* GICD */ 50 <0x1d060000 0x80000>; /* GICR */ 51 interrupt-controller; 52 #interrupt-cells = <4>; 53 status = "okay"; 54 #address-cells = <1>; 55 #size-cells = <1>; 56 57 its: msi-controller@1d040000 { 58 compatible = "arm,gic-v3-its"; 59 reg = <0x1d040000 0x20000>; 60 status = "disabled"; 61 }; 62 }; 63 64 arch_timer: timer { 65 compatible = "arm,armv8-timer"; 66 interrupt-parent = <&gic>; 67 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 68 <GIC_PPI 14 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 69 <GIC_PPI 11 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 70 <GIC_PPI 10 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 71 }; 72 73 sysmgr: sysmgr@10d12000 { 74 compatible = "syscon"; 75 reg = <0x10d12000 0x1000>; 76 }; 77 78 clock: clock@10d10000 { 79 compatible = "intel,agilex5-clock"; 80 reg = <0x10d10000 0x1000>; 81 #clock-cells = <1>; 82 }; 83 84 psci { 85 compatible = "arm,psci-1.1"; 86 method = "smc"; 87 }; 88 89 /* This is for setting the MMU region for pinmux */ 90 pinmux: pinmux@10d13000 { 91 compatible = "syscon"; 92 reg = <0x10d13000 0x1000>; 93 }; 94 95 mem0: memory@80100000 { 96 device_type = "memory"; 97 reg = <0x80100000 DT_SIZE_M(8)>; 98 }; 99 100 fpga0: bridges { 101 compatible = "altr,socfpga-agilex-bridge"; 102 }; 103 104 uart0: uart@10c02000 { 105 compatible = "ns16550"; 106 reg-shift = <2>; 107 reg = <0x10c02000 0x100>; 108 interrupt-parent = <&gic>; 109 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 110 interrupt-names = "irq_0"; 111 clock-frequency = <100000000>; 112 resets = <&reset RSTMGR_UART0_RSTLINE>; 113 status = "disabled"; 114 }; 115 116 reset: reset-controller@10D11000 { 117 compatible = "intel,socfpga-reset"; 118 reg = <0x10D11000 0x100>; 119 active-low; 120 #reset-cells = <1>; 121 status = "okay"; 122 }; 123 124 sdmmc: sdmmc@10808000 { 125 compatible = "cdns,sdhc"; 126 reg = <0x10808000 0x1000>, 127 <0x10B92000 0x1000>; 128 reg-names = "reg_base", "combo_phy"; 129 clock-frequency = <200000000>; 130 power_delay_ms = <1000>; 131 resets = <&reset RSTMGR_SDMMC_RSTLINE>, 132 <&reset RSTMGR_SDMMCECC_RSTLINE>, 133 <&reset RSTMGR_SOFTPHY_RSTLINE>; 134 status = "disabled"; 135 }; 136 137 timer0: timer@10C03000 { 138 compatible = "snps,dw-timers"; 139 interrupt-parent = <&gic>; 140 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL 141 IRQ_DEFAULT_PRIORITY>; 142 reg = <0x10c03000 0x100>; 143 clock-frequency = <100000000>; 144 resets = <&reset RSTMGR_SPTIMER0_RSTLINE>; 145 status = "disabled"; 146 }; 147 148 timer1: timer@10C03100 { 149 compatible = "snps,dw-timers"; 150 interrupt-parent = <&gic>; 151 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL 152 IRQ_DEFAULT_PRIORITY>; 153 reg = <0x10c03100 0x100>; 154 clock-frequency = <100000000>; 155 resets = <&reset RSTMGR_SPTIMER1_RSTLINE>; 156 status = "disabled"; 157 }; 158 159 timer2: timer@10D00000 { 160 compatible = "snps,dw-timers"; 161 interrupt-parent = <&gic>; 162 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL 163 IRQ_DEFAULT_PRIORITY>; 164 reg = <0x10D00000 0x100>; 165 clock-frequency = <100000000>; 166 resets = <&reset RSTMGR_L4SYSTIMER0_RSTLINE>; 167 status = "disabled"; 168 }; 169 170 timer3: timer@10D00100 { 171 compatible = "snps,dw-timers"; 172 interrupt-parent = <&gic>; 173 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL 174 IRQ_DEFAULT_PRIORITY>; 175 reg = <0x10D00100 0x100>; 176 clock-frequency = <100000000>; 177 resets = <&reset RSTMGR_L4SYSTIMER1_RSTLINE>; 178 }; 179 180 watchdog0: watchdog@10d00200 { 181 compatible = "snps,designware-watchdog"; 182 reg = <0x10d00200 0x100>; 183 clock-frequency = <100000000>; 184 resets = <&reset RSTMGR_WATCHDOG0_RSTLINE>; 185 status = "disabled"; 186 }; 187 188 watchdog1: watchdog@10d00300 { 189 compatible = "snps,designware-watchdog"; 190 reg = <0x10d00300 0x100>; 191 clock-frequency = <100000000>; 192 resets = <&reset RSTMGR_WATCHDOG1_RSTLINE>; 193 status = "disabled"; 194 }; 195 196 watchdog2: watchdog@10d00400 { 197 compatible = "snps,designware-watchdog"; 198 reg = <0x10d00400 0x100>; 199 clock-frequency = <100000000>; 200 resets = <&reset RSTMGR_WATCHDOG2_RSTLINE>; 201 status = "disabled"; 202 }; 203 204 watchdog3: watchdog@10d00500 { 205 compatible = "snps,designware-watchdog"; 206 reg = <0x10d00500 0x100>; 207 clock-frequency = <100000000>; 208 resets = <&reset RSTMGR_WATCHDOG3_RSTLINE>; 209 status = "disabled"; 210 }; 211 212 watchdog4: watchdog@10d00600 { 213 compatible = "snps,designware-watchdog"; 214 reg = <0x10d00600 0x100>; 215 clock-frequency = <100000000>; 216 resets = <&reset RSTMGR_WATCHDOG4_RSTLINE>; 217 status = "disabled"; 218 }; 219 220 sip_smc: smc{ 221 compatible = "intel,socfpga-agilex-sip-smc"; 222 method = "smc"; 223 status = "disabled"; 224 zephyr,num-clients = <2>; 225 }; 226 227 /* cadence Nand Flash controller*/ 228 nand: nand@10B80000 { 229 compatible = "cdns,nand"; 230 reg = <0x10B80000 0X10000>, 231 <0x10840000 0x10000>; 232 reg-names = "nand_reg","sdma"; 233 interrupt-parent = <&gic>; 234 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 235 resets = <&reset RSTMGR_NAND_RSTLINE>, 236 <&reset RSTMGR_SOFTPHY_RSTLINE>; 237 block-size = <0x20000>; 238 data-rate-mode = <0>; 239 status = "disabled"; 240 }; 241 242}; 243
