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/Zephyr-latest/dts/bindings/clock/
Draspberrypi,pico-pll.yaml2 # SPDX-License-Identifier: Apache-2.0
7 compatible: "raspberrypi,pico-pll"
9 include: [base.yaml, fixed-factor-clock.yaml]
12 fb-div:
19 post-div1:
23 The post clock divider.
26 post-div2:
30 The post clock divider.
/Zephyr-latest/dts/arm/raspberrypi/rpi_pico/
Drp2040.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 #include <arm/armv6-m.dtsi>
8 #include <zephyr/dt-bindings/adc/adc.h>
9 #include <zephyr/dt-bindings/gpio/gpio.h>
10 #include <zephyr/dt-bindings/clock/rpi_pico_rp2040_clock.h>
11 #include <zephyr/dt-bindings/i2c/i2c.h>
12 #include <zephyr/dt-bindings/regulator/rpi_pico.h>
13 #include <zephyr/dt-bindings/reset/rp2040_reset.h>
28 die-temp0 = &die_temp;
32 #address-cells = <1>;
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Drp2350.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/adc/adc.h>
8 #include <zephyr/dt-bindings/gpio/gpio.h>
9 #include <zephyr/dt-bindings/clock/rpi_pico_rp2350_clock.h>
10 #include <zephyr/dt-bindings/i2c/i2c.h>
11 #include <zephyr/dt-bindings/regulator/rpi_pico.h>
12 #include <zephyr/dt-bindings/reset/rp2350_reset.h>
21 die-temp0 = &die_temp;
25 #address-cells = <1>;
26 #size-cells = <0>;
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/Zephyr-latest/drivers/clock_control/
Dclock_control_rpi_pico.c2 * Copyright (c) 2022 Andrei-Edward Popa
5 * SPDX-License-Identifier: Apache-2.0
14 #include <zephyr/dt-bindings/clock/rpi_pico_rp2040_clock.h>
16 #include <zephyr/dt-bindings/clock/rpi_pico_rp2350_clock.h>
68 * Using the 'clock-names[0]' for expanding macro to frequency value.
69 * The 'clock-names[0]' is set same as label value that given to the node itself.
147 (-1)) \
151 rpi_pico_clkid_none = -1,
224 const struct clock_control_rpi_pico_config *config = dev->config; in rpi_pico_frequency_count()
226 fc_hw_t *fc0 = &config->clocks_regs->fc0; in rpi_pico_frequency_count()
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/Zephyr-latest/drivers/sdhc/
Dsdhc_esp32.c4 * SPDX-License-Identifier: Apache-2.0
81 uint32_t bus_clock; /* Value in Hz. ESP-IDF functions use kHz instead */
98 * - one is the clock generator which drives SDMMC peripheral,
99 * it can be configured using sdio_hw->clock register. It can generate
101 * - 4 clock dividers inside SDMMC peripheral, which can divide clock
105 * For cards which aren't UHS-1 or UHS-2 cards, which we don't support,
107 * Note: for non-UHS-1 cards, HS mode is optional.
118 * Of the second stage dividers, div0 is used for card 0, and div1 is used
140 sdio_hw->ctrl.dma_enable = 1; in sdmmc_host_dma_init()
141 sdio_hw->bmod.val = 0; in sdmmc_host_dma_init()
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