Lines Matching +full:post +full:- +full:div1
4 * SPDX-License-Identifier: Apache-2.0
81 uint32_t bus_clock; /* Value in Hz. ESP-IDF functions use kHz instead */
98 * - one is the clock generator which drives SDMMC peripheral,
99 * it can be configured using sdio_hw->clock register. It can generate
101 * - 4 clock dividers inside SDMMC peripheral, which can divide clock
105 * For cards which aren't UHS-1 or UHS-2 cards, which we don't support,
107 * Note: for non-UHS-1 cards, HS mode is optional.
118 * Of the second stage dividers, div0 is used for card 0, and div1 is used
140 sdio_hw->ctrl.dma_enable = 1; in sdmmc_host_dma_init()
141 sdio_hw->bmod.val = 0; in sdmmc_host_dma_init()
142 sdio_hw->bmod.sw_reset = 1; in sdmmc_host_dma_init()
143 sdio_hw->idinten.ni = 1; in sdmmc_host_dma_init()
144 sdio_hw->idinten.ri = 1; in sdmmc_host_dma_init()
145 sdio_hw->idinten.ti = 1; in sdmmc_host_dma_init()
150 sdio_hw->ctrl.use_internal_dma = 0; in sdmmc_host_dma_stop()
151 sdio_hw->ctrl.dma_reset = 1; in sdmmc_host_dma_stop()
152 sdio_hw->bmod.fb = 0; in sdmmc_host_dma_stop()
153 sdio_hw->bmod.enable = 0; in sdmmc_host_dma_stop()
158 k_mutex_init(&data->s_request_mutex); in sdmmc_host_transaction_handler_init()
160 data->s_is_app_cmd = false; in sdmmc_host_transaction_handler_init()
172 if (!data->s_host_ctx.event_queue) { in sdmmc_host_wait_for_event()
176 int ret = k_msgq_get(data->s_host_ctx.event_queue, out_event, K_MSEC(timeout_ms)); in sdmmc_host_wait_for_event()
208 if (t1 - t0 > SDMMC_HOST_WAIT_EVENT_TIMEOUT_US) { in handle_idle_state_events()
212 if (t1 - t0 > yield_delay_us) { in handle_idle_state_events()
224 if (data->s_cur_transfer.size_remaining == 0) { in fill_dma_descriptors()
228 const size_t next = data->s_cur_transfer.next_desc; in fill_dma_descriptors()
229 sdmmc_desc_t *desc = &data->s_dma_desc[next]; in fill_dma_descriptors()
231 if (desc->owned_by_idmac) { in fill_dma_descriptors()
235 size_t size_to_fill = (data->s_cur_transfer.size_remaining < SDMMC_DMA_MAX_BUF_LEN) in fill_dma_descriptors()
236 ? data->s_cur_transfer.size_remaining in fill_dma_descriptors()
239 bool last = size_to_fill == data->s_cur_transfer.size_remaining; in fill_dma_descriptors()
241 desc->last_descriptor = last; in fill_dma_descriptors()
242 desc->second_address_chained = 1; in fill_dma_descriptors()
243 desc->owned_by_idmac = 1; in fill_dma_descriptors()
244 desc->buffer1_ptr = data->s_cur_transfer.ptr; in fill_dma_descriptors()
245 desc->next_desc_ptr = in fill_dma_descriptors()
246 (last) ? NULL : &data->s_dma_desc[(next + 1) % SDMMC_DMA_DESC_CNT]; in fill_dma_descriptors()
252 desc->buffer1_size = (size_to_fill + 3) & (~3); in fill_dma_descriptors()
254 data->s_cur_transfer.size_remaining -= size_to_fill; in fill_dma_descriptors()
255 data->s_cur_transfer.ptr += size_to_fill; in fill_dma_descriptors()
256 data->s_cur_transfer.next_desc = in fill_dma_descriptors()
257 (data->s_cur_transfer.next_desc + 1) % SDMMC_DMA_DESC_CNT; in fill_dma_descriptors()
260 data->s_cur_transfer.size_remaining, data->s_cur_transfer.next_desc, in fill_dma_descriptors()
261 desc->last_descriptor, desc->buffer1_size); in fill_dma_descriptors()
302 while (sdio_hw->cmd.start_command == 1) { in sdmmc_host_start_command()
305 if (t1 - t0 > SDMMC_HOST_START_CMD_TIMEOUT_US) { in sdmmc_host_start_command()
308 if (t1 - t0 > yield_delay_us) { in sdmmc_host_start_command()
314 sdio_hw->cmdarg = arg; in sdmmc_host_start_command()
317 sdio_hw->cmd = cmd; in sdmmc_host_start_command()
325 if (cmd->flags & SCF_RSP_PRESENT) { in process_command_response()
326 if (cmd->flags & SCF_RSP_136) { in process_command_response()
327 /* Destination is 4-byte aligned, can memcopy from peripheral registers */ in process_command_response()
328 memcpy(cmd->response, (uint32_t *)sdio_hw->resp, 4 * sizeof(uint32_t)); in process_command_response()
330 cmd->response[0] = sdio_hw->resp[0]; in process_command_response()
331 cmd->response[1] = 0; in process_command_response()
332 cmd->response[2] = 0; in process_command_response()
333 cmd->response[3] = 0; in process_command_response()
341 if (!(cmd->flags & SCF_RSP_PRESENT)) { in process_command_response()
346 } else if ((cmd->flags & SCF_RSP_CRC) && (status & SDMMC_INTMASK_RCRC)) { in process_command_response()
353 cmd->error = err; in process_command_response()
354 if (cmd->data) { in process_command_response()
365 cmd->error = ESP_ERR_TIMEOUT; in process_data_status()
367 cmd->error = ESP_ERR_INVALID_CRC; in process_data_status()
368 } else if ((status & SDMMC_INTMASK_EBE) && (cmd->flags & SCF_CMD_READ) == 0) { in process_data_status()
369 cmd->error = ESP_ERR_TIMEOUT; in process_data_status()
371 cmd->error = ESP_FAIL; in process_data_status()
373 sdio_hw->ctrl.fifo_reset = 1; in process_data_status()
376 if (cmd->error != 0) { in process_data_status()
377 if (cmd->data) { in process_data_status()
380 LOG_DBG("%s: error 0x%x (status=%08" PRIx32 ")", __func__, cmd->error, status); in process_data_status()
395 const size_t next = data->s_cur_transfer.next_desc; in get_free_descriptors_count()
403 sdmmc_desc_t *desc = &data->s_dma_desc[(next + i) % SDMMC_DMA_DESC_CNT]; in get_free_descriptors_count()
405 if (desc->owned_by_idmac) { in get_free_descriptors_count()
409 if (desc->next_desc_ptr == NULL) { in get_free_descriptors_count()
422 const struct sdhc_esp32_config *cfg = dev->config; in process_events()
423 struct sdhc_esp32_data *data = dev->data; in process_events()
424 sdmmc_dev_t *sdio_hw = (sdmmc_dev_t *)cfg->sdio_hw; in process_events()
434 enum sdmmc_req_state state = (enum sdmmc_req_state) -1; in process_events()
456 if (cmd->error != ESP_OK) { in process_events()
461 if (cmd->data == NULL) { in process_events()
476 data->s_cur_transfer.desc_remaining--; in process_events()
478 if (data->s_cur_transfer.size_remaining) { in process_events()
485 if (data->s_cur_transfer.desc_remaining == 0) { in process_events()
517 const struct sdhc_esp32_config *cfg = dev->config; in handle_event()
518 struct sdhc_esp32_data *data = dev->data; in handle_event()
519 sdmmc_dev_t *sdio_hw = (sdmmc_dev_t *)cfg->sdio_hw; in handle_event()
522 int err = sdmmc_host_wait_for_event(data, cmd->timeout_ms, &event); in handle_event()
527 err, cmd->timeout_ms); in handle_event()
528 if (err == -EAGAIN) { in handle_event()
536 event.sdmmc_status, event.dma_status, unhandled_events->sdmmc_status, in handle_event()
537 unhandled_events->dma_status); in handle_event()
539 event.sdmmc_status |= unhandled_events->sdmmc_status; in handle_event()
540 event.dma_status |= unhandled_events->dma_status; in handle_event()
544 unhandled_events->sdmmc_status, unhandled_events->dma_status); in handle_event()
552 return !(sdio_hw->status.data_busy == 1); in wait_for_busy_cleared()
561 while (timeout_ticks-- > 0) { in wait_for_busy_cleared()
562 if (!(sdio_hw->status.data_busy == 1)) { in wait_for_busy_cleared()
574 return cmd->datalen > 0 && in cmd_needs_auto_stop()
575 (cmd->opcode == SD_WRITE_MULTIPLE_BLOCK || cmd->opcode == SD_READ_MULTIPLE_BLOCK); in cmd_needs_auto_stop()
582 res.cmd_index = cmd->opcode; in make_hw_cmd()
583 if (cmd->opcode == SD_STOP_TRANSMISSION) { in make_hw_cmd()
585 } else if (cmd->opcode == SD_GO_IDLE_STATE) { in make_hw_cmd()
590 if (cmd->opcode == SD_GO_IDLE_STATE) { in make_hw_cmd()
593 if (cmd->flags & SCF_RSP_PRESENT) { in make_hw_cmd()
595 if (cmd->flags & SCF_RSP_136) { in make_hw_cmd()
599 if (cmd->flags & SCF_RSP_CRC) { in make_hw_cmd()
602 if (cmd->data) { in make_hw_cmd()
605 if ((cmd->flags & SCF_CMD_READ) == 0) { in make_hw_cmd()
609 if ((cmd->datalen % cmd->blklen) != 0) { in make_hw_cmd()
624 const struct sdhc_esp32_config *cfg = dev->config; in sdmmc_host_do_transaction()
625 struct sdhc_esp32_data *data = dev->data; in sdmmc_host_do_transaction()
626 sdmmc_dev_t *sdio_hw = (sdmmc_dev_t *)cfg->sdio_hw; in sdmmc_host_do_transaction()
629 if (k_mutex_lock(&data->s_request_mutex, K_FOREVER) != 0) { in sdmmc_host_do_transaction()
639 if (cmdinfo->data) { in sdmmc_host_do_transaction()
641 if ((cmdinfo->datalen >= 4) && (cmdinfo->datalen % 4) != 0) { in sdmmc_host_do_transaction()
642 LOG_DBG("%s: invalid size: total=%d", __func__, cmdinfo->datalen); in sdmmc_host_do_transaction()
647 if ((((intptr_t)cmdinfo->data % 4) != 0) || !esp_ptr_dma_capable(cmdinfo->data)) { in sdmmc_host_do_transaction()
648 LOG_DBG("%s: buffer %p can not be used for DMA", __func__, cmdinfo->data); in sdmmc_host_do_transaction()
654 memset(data->s_dma_desc, 0, sizeof(data->s_dma_desc)); in sdmmc_host_do_transaction()
657 data->s_dma_desc[0].first_descriptor = 1; in sdmmc_host_do_transaction()
660 data->s_cur_transfer.ptr = (uint8_t *)cmdinfo->data; in sdmmc_host_do_transaction()
661 data->s_cur_transfer.size_remaining = cmdinfo->datalen; in sdmmc_host_do_transaction()
662 data->s_cur_transfer.next_desc = 0; in sdmmc_host_do_transaction()
663 data->s_cur_transfer.desc_remaining = in sdmmc_host_do_transaction()
664 (cmdinfo->datalen + SDMMC_DMA_MAX_BUF_LEN - 1) / SDMMC_DMA_MAX_BUF_LEN; in sdmmc_host_do_transaction()
670 sdmmc_host_dma_prepare(sdio_hw, &data->s_dma_desc[0], cmdinfo->blklen, in sdmmc_host_do_transaction()
671 cmdinfo->datalen); in sdmmc_host_do_transaction()
675 ret = sdmmc_host_start_command(sdio_hw, slot, hw_cmd, cmdinfo->arg); in sdmmc_host_do_transaction()
682 cmdinfo->error = ESP_OK; in sdmmc_host_do_transaction()
694 if (ret == 0 && (cmdinfo->flags & SCF_WAIT_BUSY)) { in sdmmc_host_do_transaction()
695 if (!wait_for_busy_cleared(sdio_hw, cmdinfo->timeout_ms)) { in sdmmc_host_do_transaction()
700 data->s_is_app_cmd = (ret == ESP_OK && cmdinfo->opcode == SD_APP_CMD); in sdmmc_host_do_transaction()
704 k_mutex_unlock(&data->s_request_mutex); in sdmmc_host_do_transaction()
732 if (t1 - t0 > SDMMC_HOST_CLOCK_UPDATE_CMD_TIMEOUT_US) { in sdmmc_host_clock_update_command()
737 if (sdio_hw->rintsts.hle) { in sdmmc_host_clock_update_command()
738 sdio_hw->rintsts.hle = 1; in sdmmc_host_clock_update_command()
743 /* cleared in sdio_hw->cmd register */ in sdmmc_host_clock_update_command()
744 if (sdio_hw->cmd.start_command == 0) { in sdmmc_host_clock_update_command()
748 if (t1 - t0 > yield_delay_us) { in sdmmc_host_clock_update_command()
778 * for custom frequencies use maximum range of host divider (1-16), find the closest in sdmmc_host_get_clk_dividers()
781 * - 32 MHz (32.1 - 39.9 MHz cannot be covered with given divider scheme) in sdmmc_host_get_clk_dividers()
823 int host_div = 0; /* clock divider of the host (sdio_hw->clock) */ in sdmmc_host_set_card_clk()
824 int card_div = 0; /* 1/2 of card clock divider (sdio_hw->clkdiv) */ in sdmmc_host_set_card_clk()
849 /* Re-enable clocks */ in sdmmc_host_set_card_clk()
856 LOG_ERR("re-enabling clk failed"); in sdmmc_host_set_card_clk()
881 sdio_hw->ctype.card_width_8 &= ~mask; in sdmmc_host_set_bus_width()
882 sdio_hw->ctype.card_width &= ~mask; in sdmmc_host_set_bus_width()
884 sdio_hw->ctype.card_width_8 &= ~mask; in sdmmc_host_set_bus_width()
885 sdio_hw->ctype.card_width |= mask; in sdmmc_host_set_bus_width()
924 const struct sdhc_esp32_config *cfg = dev->config; in sdhc_esp32_reset()
925 sdmmc_dev_t *sdio_hw = (sdmmc_dev_t *)cfg->sdio_hw; in sdhc_esp32_reset()
928 sdio_hw->ctrl.controller_reset = 1; in sdhc_esp32_reset()
929 sdio_hw->ctrl.dma_reset = 1; in sdhc_esp32_reset()
930 sdio_hw->ctrl.fifo_reset = 1; in sdhc_esp32_reset()
937 while (sdio_hw->ctrl.controller_reset || sdio_hw->ctrl.fifo_reset || in sdhc_esp32_reset()
938 sdio_hw->ctrl.dma_reset) { in sdhc_esp32_reset()
941 if (t1 - t0 > SDMMC_HOST_RESET_TIMEOUT_US) { in sdhc_esp32_reset()
942 return -ETIMEDOUT; in sdhc_esp32_reset()
945 if (t1 - t0 > yield_delay_us) { in sdhc_esp32_reset()
960 const struct sdhc_esp32_config *cfg = dev->config; in sdhc_esp32_set_io()
961 sdmmc_dev_t *sdio_hw = (sdmmc_dev_t *)cfg->sdio_hw; in sdhc_esp32_set_io()
962 struct sdhc_esp32_data *data = dev->data; in sdhc_esp32_set_io()
967 cfg->slot, ios->bus_width, ios->clock, in sdhc_esp32_set_io()
968 ios->power_mode == SDHC_POWER_ON ? "ON" : "OFF", in sdhc_esp32_set_io()
969 ios->signal_voltage == SD_VOL_1_8_V ? "1.8V" : "3.3V"); in sdhc_esp32_set_io()
971 if (ios->clock) { in sdhc_esp32_set_io()
973 if (ios->clock > cfg->props.f_max || ios->clock < cfg->props.f_min) { in sdhc_esp32_set_io()
975 return -EINVAL; in sdhc_esp32_set_io()
978 if (data->bus_clock != (uint32_t)ios->clock) { in sdhc_esp32_set_io()
980 ret = sdmmc_host_set_card_clk(sdio_hw, cfg->slot, (ios->clock / 1000)); in sdhc_esp32_set_io()
983 LOG_INF("Bus clock successfully set to %d kHz", ios->clock / 1000); in sdhc_esp32_set_io()
989 data->bus_clock = (uint32_t)ios->clock; in sdhc_esp32_set_io()
993 if (ios->bus_width > 0) { in sdhc_esp32_set_io()
995 switch (ios->bus_width) { in sdhc_esp32_set_io()
1003 return -ENOTSUP; in sdhc_esp32_set_io()
1006 if (data->bus_width != bus_width) { in sdhc_esp32_set_io()
1007 ret = sdmmc_host_set_bus_width(sdio_hw, cfg->slot, bus_width); in sdhc_esp32_set_io()
1016 data->bus_width = bus_width; in sdhc_esp32_set_io()
1021 if ((data->power_mode != ios->power_mode) && (cfg->pwr_gpio.port)) { in sdhc_esp32_set_io()
1022 if (ios->power_mode == SDHC_POWER_OFF) { in sdhc_esp32_set_io()
1023 gpio_pin_set_dt(&cfg->pwr_gpio, 0); in sdhc_esp32_set_io()
1024 } else if (ios->power_mode == SDHC_POWER_ON) { in sdhc_esp32_set_io()
1025 gpio_pin_set_dt(&cfg->pwr_gpio, 1); in sdhc_esp32_set_io()
1027 data->power_mode = ios->power_mode; in sdhc_esp32_set_io()
1030 if (ios->timing > 0) { in sdhc_esp32_set_io()
1032 if (data->timing != ios->timing) { in sdhc_esp32_set_io()
1033 switch (ios->timing) { in sdhc_esp32_set_io()
1036 sdmmc_ll_enable_ddr_mode(sdio_hw, cfg->slot, false); in sdhc_esp32_set_io()
1041 sdmmc_ll_enable_ddr_mode(sdio_hw, cfg->slot, true); in sdhc_esp32_set_io()
1046 sdmmc_ll_enable_ddr_mode(sdio_hw, cfg->slot, false); in sdhc_esp32_set_io()
1054 ret = -ENOTSUP; in sdhc_esp32_set_io()
1058 LOG_INF("Bus timing successfully changed to %s", timingStr[ios->timing]); in sdhc_esp32_set_io()
1059 data->timing = ios->timing; in sdhc_esp32_set_io()
1071 const struct sdhc_esp32_config *cfg = dev->config; in sdhc_esp32_card_busy()
1072 const sdmmc_dev_t *sdio_hw = cfg->sdio_hw; in sdhc_esp32_card_busy()
1074 return (sdio_hw->status.data_busy == 1); in sdhc_esp32_card_busy()
1083 const struct sdhc_esp32_config *cfg = dev->config; in sdhc_esp32_request()
1084 int retries = (int)(cmd->retries + 1); /* first try plus retries */ in sdhc_esp32_request()
1091 .opcode = cmd->opcode, in sdhc_esp32_request()
1092 .arg = cmd->arg, in sdhc_esp32_request()
1096 esp_cmd.data = data->data; in sdhc_esp32_request()
1097 esp_cmd.blklen = data->block_size; in sdhc_esp32_request()
1098 esp_cmd.datalen = (data->blocks * data->block_size); in sdhc_esp32_request()
1100 timeout_cfg = data->timeout_ms; in sdhc_esp32_request()
1102 timeout_cfg = cmd->timeout_ms; in sdhc_esp32_request()
1106 if (cmd->timeout_ms == SDHC_TIMEOUT_FOREVER) { in sdhc_esp32_request()
1115 switch (cmd->opcode) { in sdhc_esp32_request()
1157 /* Don't expect to see a response when de-selecting a card */ in sdhc_esp32_request()
1158 esp_cmd.flags = SCF_CMD_AC | (cmd->arg > 0 ? SCF_RSP_R1 : 0); in sdhc_esp32_request()
1175 LOG_INF("SDHC driver: command %u not supported", cmd->opcode); in sdhc_esp32_request()
1176 return -ENOTSUP; in sdhc_esp32_request()
1181 ret_esp = sdmmc_host_do_transaction(dev, cfg->slot, &esp_cmd); in sdhc_esp32_request()
1184 retries--; /* error, retry */ in sdhc_esp32_request()
1192 cmd->opcode, cmd->arg, ret_esp, esp_cmd.error); in sdhc_esp32_request()
1199 memcpy(cmd->response, esp_cmd.response, sizeof(cmd->response)); in sdhc_esp32_request()
1209 data->bytes_xfered = esp_cmd.datalen; in sdhc_esp32_request()
1221 const struct sdhc_esp32_config *cfg = dev->config; in sdhc_esp32_get_card_present()
1222 sdmmc_dev_t *sdio_hw = (sdmmc_dev_t *)cfg->sdio_hw; in sdhc_esp32_get_card_present()
1224 return sdmmc_ll_is_card_detected(sdio_hw, cfg->slot); in sdhc_esp32_get_card_present()
1232 const struct sdhc_esp32_config *cfg = dev->config; in sdhc_esp32_get_host_props()
1234 memcpy(props, &cfg->props, sizeof(struct sdhc_host_props)); in sdhc_esp32_get_host_props()
1256 const struct sdhc_esp32_config *cfg = dev->config; in sdio_esp32_isr()
1257 struct sdhc_esp32_data *data = dev->data; in sdio_esp32_isr()
1258 sdmmc_dev_t *sdio_hw = (sdmmc_dev_t *)cfg->sdio_hw; in sdio_esp32_isr()
1261 struct k_msgq *queue = data->s_host_ctx.event_queue; in sdio_esp32_isr()
1264 sdio_hw->rintsts.val = pending; in sdio_esp32_isr()
1267 uint32_t dma_pending = sdio_hw->idsts.val; in sdio_esp32_isr()
1269 sdio_hw->idsts.val = dma_pending; in sdio_esp32_isr()
1282 const struct sdhc_esp32_config *cfg = dev->config; in sdhc_esp32_init()
1283 struct sdhc_esp32_data *data = dev->data; in sdhc_esp32_init()
1284 sdmmc_dev_t *sdio_hw = (sdmmc_dev_t *)cfg->sdio_hw; in sdhc_esp32_init()
1290 if (cfg->pwr_gpio.port) { in sdhc_esp32_init()
1291 ret = gpio_pin_configure_dt(&cfg->pwr_gpio, GPIO_OUTPUT_ACTIVE); in sdhc_esp32_init()
1294 return -EIO; in sdhc_esp32_init()
1302 configure_pin_iomux(cfg->clk_pin); in sdhc_esp32_init()
1303 configure_pin_iomux(cfg->cmd_pin); in sdhc_esp32_init()
1304 configure_pin_iomux(cfg->d0_pin); in sdhc_esp32_init()
1305 configure_pin_iomux(cfg->d1_pin); in sdhc_esp32_init()
1306 configure_pin_iomux(cfg->d2_pin); in sdhc_esp32_init()
1307 configure_pin_iomux(cfg->d3_pin); in sdhc_esp32_init()
1309 ret = pinctrl_apply_state(cfg->pcfg, PINCTRL_STATE_DEFAULT); in sdhc_esp32_init()
1313 return -EINVAL; in sdhc_esp32_init()
1316 if (!device_is_ready(cfg->clock_dev)) { in sdhc_esp32_init()
1317 return -ENODEV; in sdhc_esp32_init()
1320 ret = clock_control_on(cfg->clock_dev, cfg->clock_subsys); in sdhc_esp32_init()
1338 sdio_hw->rintsts.val = 0xffffffff; in sdhc_esp32_init()
1339 sdio_hw->intmask.val = 0; in sdhc_esp32_init()
1340 sdio_hw->ctrl.int_enable = 0; in sdhc_esp32_init()
1343 ret = esp_intr_alloc(cfg->irq_source, in sdhc_esp32_init()
1344 ESP_PRIO_TO_FLAGS(cfg->irq_priority) | in sdhc_esp32_init()
1345 ESP_INT_FLAGS_CHECK(cfg->irq_flags) | ESP_INTR_FLAG_IRAM, in sdhc_esp32_init()
1347 &data->s_host_ctx.intr_handle); in sdhc_esp32_init()
1350 k_msgq_purge(data->s_host_ctx.event_queue); in sdhc_esp32_init()
1351 return -EFAULT; in sdhc_esp32_init()
1355 sdio_hw->intmask.val = SDMMC_INTMASK_CD | SDMMC_INTMASK_CMD_DONE | SDMMC_INTMASK_DATA_OVER | in sdhc_esp32_init()
1361 sdio_hw->ctrl.int_enable = 1; in sdhc_esp32_init()
1364 sdio_hw->cardthrctl.busy_clr_int_en = 0; in sdhc_esp32_init()
1373 k_msgq_purge(data->s_host_ctx.event_queue); in sdhc_esp32_init()
1374 esp_intr_free(data->s_host_ctx.intr_handle); in sdhc_esp32_init()
1375 data->s_host_ctx.intr_handle = NULL; in sdhc_esp32_init()
1380 /* post init settings */ in sdhc_esp32_init()
1381 ret = sdmmc_host_set_card_clk(sdio_hw, cfg->slot, data->bus_clock / 1000); in sdhc_esp32_init()
1388 ret = sdmmc_host_set_bus_width(sdio_hw, cfg->slot, data->bus_width); in sdhc_esp32_init()
1467 "Currently, only one espressif,esp32-sdhc-slot compatible node is supported");