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/Zephyr-latest/drivers/gpio/
Dgpio_ambiq.c44 am_hal_gpio_pincfg_t pincfg = g_AM_HAL_GPIO_DEFAULT; in ambiq_gpio_pin_configure() local
47 pincfg = g_AM_HAL_GPIO_INPUT; in ambiq_gpio_pin_configure()
49 pincfg.ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K; in ambiq_gpio_pin_configure()
51 pincfg.ePullup = AM_HAL_GPIO_PIN_PULLDOWN; in ambiq_gpio_pin_configure()
57 pincfg.eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN; in ambiq_gpio_pin_configure()
59 pincfg.ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K; in ambiq_gpio_pin_configure()
61 pincfg.ePullup = AM_HAL_GPIO_PIN_PULLDOWN; in ambiq_gpio_pin_configure()
65 pincfg.eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL; in ambiq_gpio_pin_configure()
69 pincfg = g_AM_HAL_GPIO_DEFAULT; in ambiq_gpio_pin_configure()
73 pincfg.eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVEHIGH; in ambiq_gpio_pin_configure()
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Dgpio_renesas_ra.c147 struct ra_pinctrl_soc_pin pincfg = {0}; in gpio_ra_pin_configure() local
158 pincfg.cfg |= BIT(R_PFS_PORT_PIN_PmnPFS_PDR_Pos); in gpio_ra_pin_configure()
162 pincfg.cfg |= BIT(R_PFS_PORT_PIN_PmnPFS_PCR_Pos); in gpio_ra_pin_configure()
166 pincfg.cfg |= BIT(R_PFS_PORT_PIN_PmnPFS_NCODR_Pos); in gpio_ra_pin_configure()
170 pincfg.cfg |= BIT(R_PFS_PORT_PIN_PmnPFS_ISEL_Pos); in gpio_ra_pin_configure()
173 pincfg.cfg &= ~BIT(R_PFS_PORT_PIN_PmnPFS_PMR_Pos); in gpio_ra_pin_configure()
175 pincfg.pin_num = pin; in gpio_ra_pin_configure()
176 pincfg.port_num = config->port; in gpio_ra_pin_configure()
225 return pinctrl_configure_pins(&pincfg, 1, PINCTRL_REG_NONE); in gpio_ra_pin_configure()
233 struct ra_pinctrl_soc_pin pincfg; in gpio_ra_pin_get_config() local
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Dgpio_sam0.c57 PORT_PINCFG_Type pincfg = { in gpio_sam0_config() local
67 pincfg.bit.INEN = 1; in gpio_sam0_config()
87 pincfg.bit.PULLEN = 1; in gpio_sam0_config()
99 && (pincfg.bit.INEN != 0)); in gpio_sam0_config()
102 regs->PINCFG[pin] = pincfg; in gpio_sam0_config()
169 PORT_PINCFG_Type pincfg = { in gpio_sam0_pin_interrupt_configure() local
170 .reg = regs->PINCFG[pin].reg, in gpio_sam0_pin_interrupt_configure()
179 pincfg.bit.PMUXEN = 0; in gpio_sam0_pin_interrupt_configure()
198 if ((pincfg.bit.INEN == 0) in gpio_sam0_pin_interrupt_configure()
205 pincfg.bit.PMUXEN = 1; in gpio_sam0_pin_interrupt_configure()
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/Zephyr-latest/soc/nordic/common/
Dpinctrl_soc.h102 * @param pincfg Pin configuration bit field.
104 #define NRF_GET_FUN(pincfg) (((pincfg) >> NRF_FUN_POS) & NRF_FUN_MSK) argument
109 * @param pincfg Pin configuration bit field.
111 #define NRF_GET_CLOCKPIN_ENABLE(pincfg) \ argument
112 (((pincfg) >> NRF_CLOCKPIN_ENABLE_POS) & NRF_CLOCKPIN_ENABLE_MSK)
117 * @param pincfg Pin configuration bit field.
119 #define NRF_GET_GPD_FAST_ACTIVE1(pincfg) \ argument
120 (((pincfg) >> NRF_GPD_FAST_ACTIVE1_POS) & NRF_GPD_FAST_ACTIVE1_MSK)
125 * @param pincfg Pin configuration bit field.
127 #define NRF_GET_INVERT(pincfg) (((pincfg) >> NRF_INVERT_POS) & NRF_INVERT_MSK) argument
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/Zephyr-latest/drivers/pinctrl/
Dpinctrl_max32.c31 int pincfg; in pinctrl_configure_pin() local
37 pincfg = soc_pin.pincfg; in pinctrl_configure_pin()
46 if (pincfg & BIT(MAX32_BIAS_PULL_UP_SHIFT)) { in pinctrl_configure_pin()
48 } else if (pincfg & BIT(MAX32_BIAS_PULL_DOWN_SHIFT)) { in pinctrl_configure_pin()
54 if (pincfg & BIT(MAX32_INPUT_ENABLE_SHIFT)) { in pinctrl_configure_pin()
56 } else if (pincfg & BIT(MAX32_OUTPUT_ENABLE_SHIFT)) { in pinctrl_configure_pin()
63 if (pincfg & BIT(MAX32_POWER_SOURCE_SHIFT)) { in pinctrl_configure_pin()
69 gpio_cfg.drvstr = (pincfg >> MAX32_DRV_STRENGTH_SHIFT) & MAX32_DRV_STRENGTH_MASK; in pinctrl_configure_pin()
75 if (pincfg & BIT(MAX32_OUTPUT_ENABLE_SHIFT)) { in pinctrl_configure_pin()
76 if (pincfg & BIT(MAX32_OUTPUT_HIGH_SHIFT)) { in pinctrl_configure_pin()
Dpinctrl_ite_it8xxx2.c76 uint32_t pincfg = pins->pincfg; in pinctrl_it8xxx2_set() local
83 switch (IT8XXX2_DT_PINCFG_PUPDR(pincfg)) { in pinctrl_it8xxx2_set()
108 switch (IT8XXX2_DT_PINCFG_VOLTAGE(pincfg)) { in pinctrl_it8xxx2_set()
114 __ASSERT(!(IT8XXX2_DT_PINCFG_PUPDR(pincfg) in pinctrl_it8xxx2_set()
127 if (IT8XXX2_DT_PINCFG_IMPEDANCE(pincfg)) { in pinctrl_it8xxx2_set()
134 IT8XXX2_DT_PINCFG_DRIVE_CURRENT(pincfg) != IT8XXX2_DRIVE_DEFAULT) { in pinctrl_it8xxx2_set()
135 if (IT8XXX2_DT_PINCFG_DRIVE_CURRENT(pincfg) & IT8XXX2_PDSCX_MASK) { in pinctrl_it8xxx2_set()
171 * If pincfg is input, we don't need to handle in pinctrl_gpio_it8xxx2_configure_pins()
174 if (IT8XXX2_DT_PINCFG_INPUT(pins->pincfg)) { in pinctrl_gpio_it8xxx2_configure_pins()
239 uint32_t pincfg = pins->pincfg; in pinctrl_kscan_it8xxx2_set() local
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Dpinctrl_ti_cc32xx.c24 static int pinctrl_configure_pin(pinctrl_soc_pin_t pincfg) in pinctrl_configure_pin() argument
28 pin = (pincfg >> TI_CC32XX_PIN_POS) & TI_CC32XX_PIN_MSK; in pinctrl_configure_pin()
33 sys_write32(pincfg & MEM_GPIO_PAD_CONFIG_MSK, DT_INST_REG_ADDR(0) + (pin2pad[pin] << 2U)); in pinctrl_configure_pin()
/Zephyr-latest/soc/silabs/common/
Dpinctrl_soc.h114 * @param pincfg Pin configuration bit field.
116 #define GECKO_GET_FUN(pincfg) (((pincfg) >> GECKO_FUN_POS) & GECKO_FUN_MSK)
121 * @param pincfg port configuration bit field.
123 #define GECKO_GET_PORT(pincfg) (((pincfg) >> GECKO_PORT_POS) & GECKO_PORT_MSK)
128 * @param pincfg pin configuration bit field.
130 #define GECKO_GET_PIN(pincfg) (((pincfg) >> GECKO_PIN_POS) & GECKO_PIN_MSK)
135 * @param pincfg Loc configuration bit field.
137 #define GECKO_GET_LOC(pincfg) (((pincfg) >> GECKO_LOC_POS) & GECKO_LOC_MSK)
142 * @param pincfg speed configuration bit field.
144 #define GECKO_GET_SPEED(pincfg) (((pincfg) >> GECKO_SPEED_POS) & GECKO_SPEED_MSK)
/Zephyr-latest/soc/atmel/sam0/common/
Dsoc_port.c30 pg->PINCFG[pin].bit.PMUXEN = 1; in soc_port_pinmux_set()
40 PORT_PINCFG_Type pincfg = { .reg = 0 }; in soc_port_configure() local
43 pg->PINCFG[pin->pinum] = pincfg; in soc_port_configure()
57 pincfg.bit.PULLEN = 1; in soc_port_configure()
61 pincfg.bit.INEN = 1; in soc_port_configure()
69 pincfg.bit.DRVSTR = 1; in soc_port_configure()
72 pg->PINCFG[pin->pinum] = pincfg; in soc_port_configure()
/Zephyr-latest/drivers/pinctrl/renesas/ra/
Dpinctrl_ra.c30 int ra_pinctrl_query_config(uint32_t port, uint32_t pin, pinctrl_soc_pin_t *pincfg) in ra_pinctrl_query_config() argument
36 pincfg->port_num = port; in ra_pinctrl_query_config()
37 pincfg->pin_num = pin; in ra_pinctrl_query_config()
39 pincfg->cfg = R_PFS->PORT[port].PIN[pin].PmnPFS; in ra_pinctrl_query_config()
/Zephyr-latest/tests/drivers/pinctrl/api/src/
Dpinctrl_soc.h55 * @param pincfg Pin configuration bit field.
57 #define TEST_GET_PULL(pincfg) (((pincfg) >> TEST_PULL_POS) & TEST_PULL_MSK) argument
62 * @param pincfg Pin configuration bit field.
64 #define TEST_GET_PIN(pincfg) (((pincfg) >> TEST_PIN_POS) & TEST_PIN_MSK) argument
/Zephyr-latest/soc/gd/gd32/common/
Dpinctrl_soc.h169 * @param pincfg pinctrl_soc_pin_t bit field value.
171 #define GD32_PUPD_GET(pincfg) \ argument
172 (((pincfg) >> GD32_PUPD_POS) & GD32_PUPD_MSK)
177 * @param pincfg pinctrl_soc_pin_t bit field value.
179 #define GD32_OTYPE_GET(pincfg) \ argument
180 (((pincfg) >> GD32_OTYPE_POS) & GD32_OTYPE_MSK)
185 * @param pincfg pinctrl_soc_pin_t bit field value.
187 #define GD32_OSPEED_GET(pincfg) \ argument
188 (((pincfg) >> GD32_OSPEED_POS) & GD32_OSPEED_MSK)
/Zephyr-latest/drivers/memc/
Dmemc_renesas_ra_sdram.c16 const struct pinctrl_dev_config *pincfg; member
24 err = pinctrl_apply_state(config->pincfg, PINCTRL_STATE_DEFAULT); in renesas_ra_sdram_init()
37 .pincfg = PINCTRL_DT_INST_DEV_CONFIG_GET(0),
/Zephyr-latest/include/zephyr/drivers/pinctrl/
Dpinctrl_soc_sam_common.h102 * @param pincfg pinctrl_soc_pin_t bit field value.
105 #define SAM_PINCTRL_FLAG_GET(pincfg, pos) \ argument
106 (((pincfg) >> pos) & SAM_PINCTRL_FLAG_MASK)
108 #define SAM_PINCTRL_FLAGS_GET(pincfg) \ argument
109 (((pincfg) >> SAM_PINCTRL_FLAGS_POS) & SAM_PINCTRL_FLAGS_MASK)
/Zephyr-latest/soc/espressif/esp32/
Dpinctrl_soc.h26 /** Pincfg settings (bias). */
27 uint32_t pincfg; member
38 * @brief Utility macro to initialize pincfg field in #pinctrl_pin_t.
62 .pincfg = Z_PINCTRL_ESP32_PINCFG_INIT(node_id)},
/Zephyr-latest/soc/espressif/esp32c2/
Dpinctrl_soc.h26 /** Pincfg settings (bias). */
27 uint32_t pincfg; member
38 * @brief Utility macro to initialize pincfg field in #pinctrl_pin_t.
62 .pincfg = Z_PINCTRL_ESP32_PINCFG_INIT(node_id)},
/Zephyr-latest/soc/espressif/esp32c3/
Dpinctrl_soc.h26 /** Pincfg settings (bias). */
27 uint32_t pincfg; member
38 * @brief Utility macro to initialize pincfg field in #pinctrl_pin_t.
62 .pincfg = Z_PINCTRL_ESP32_PINCFG_INIT(node_id)},
/Zephyr-latest/soc/espressif/esp32c6/
Dpinctrl_soc.h26 /** Pincfg settings (bias). */
27 uint32_t pincfg; member
39 * @brief Utility macro to initialize pincfg field in #pinctrl_pin_t.
63 .pincfg = Z_PINCTRL_ESP32_PINCFG_INIT(node_id) },
/Zephyr-latest/soc/espressif/esp32s2/
Dpinctrl_soc.h26 /** Pincfg settings (bias). */
27 uint32_t pincfg; member
38 * @brief Utility macro to initialize pincfg field in #pinctrl_pin_t.
62 .pincfg = Z_PINCTRL_ESP32_PINCFG_INIT(node_id)},
/Zephyr-latest/soc/espressif/esp32s3/
Dpinctrl_soc.h26 /** Pincfg settings (bias). */
27 uint32_t pincfg; member
40 * @brief Utility macro to initialize pincfg field in #pinctrl_pin_t.
64 .pincfg = Z_PINCTRL_ESP32_PINCFG_INIT(node_id)},
/Zephyr-latest/soc/infineon/cat1a/psoc6_legacy/
Dpinctrl_soc.h50 /* Push-Pull means Strong, see dts/pinctrl/pincfg-node.yaml */
54 /* Input-Enable means Input-Buffer, see dts/pinctrl/pincfg-node.yaml */
72 uint32_t pincfg; member
86 * @brief Utility macro to initialize pincfg field in #pinctrl_pin_t.
108 .pincfg = Z_PINCTRL_CAT1_PINCFG_INIT( \
/Zephyr-latest/soc/infineon/cat1a/common/
Dpinctrl_soc.h54 /* Push-Pull means Strong, see dts/pinctrl/pincfg-node.yaml */
58 /* Input-Enable means Input-Buffer, see dts/pinctrl/pincfg-node.yaml */
76 uint32_t pincfg; member
93 * @brief Utility macro to initialize pincfg field in #pinctrl_pin_t.
115 .pincfg = Z_PINCTRL_CAT1_PINCFG_INIT( \
/Zephyr-latest/soc/infineon/cat1b/common/
Dpinctrl_soc.h54 /* Push-Pull means Strong, see dts/pinctrl/pincfg-node.yaml */
58 /* Input-Enable means Input-Buffer, see dts/pinctrl/pincfg-node.yaml */
76 uint32_t pincfg; member
93 * @brief Utility macro to initialize pincfg field in #pinctrl_pin_t.
115 .pincfg = Z_PINCTRL_CAT1_PINCFG_INIT( \
/Zephyr-latest/drivers/mdio/
Dmdio_nxp_s32_netc.c18 const struct pinctrl_dev_config *pincfg; member
60 err = pinctrl_apply_state(cfg->pincfg, PINCTRL_STATE_DEFAULT); in nxp_s32_mdio_initialize()
85 .pincfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n), \
/Zephyr-latest/drivers/ethernet/eth_nxp_enet_qos/
Deth_nxp_enet_qos.c27 return pinctrl_apply_state(config->pincfg, PINCTRL_STATE_DEFAULT); in nxp_enet_qos_init()
34 .pincfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n), \

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