1 /* 2 * Copyright (c) 2016-2017 Piotr Mienkowski 3 * Copyright (c) 2021 ATL Electronics 4 * Copyright (c) 2022 Cypress Semiconductor Corporation (an Infineon company) or 5 * an affiliate of Cypress Semiconductor Corporation 6 * 7 * SPDX-License-Identifier: Apache-2.0 8 * 9 */ 10 11 /** 12 * @brief Infineon CAT1 SoC specific helpers for pinctrl driver. 13 */ 14 15 #ifndef ZEPHYR_SOC_ARM_INFINEON_CAT1_COMMON_PINCTRL_SOC_H_ 16 #define ZEPHYR_SOC_ARM_INFINEON_CAT1_COMMON_PINCTRL_SOC_H_ 17 18 #include <stdint.h> 19 #include <zephyr/devicetree.h> 20 21 #ifdef __cplusplus 22 extern "C" { 23 #endif 24 25 /** @cond INTERNAL_HIDDEN */ 26 27 /** 28 * Bit definition in PINMUX field 29 */ 30 #define SOC_PINMUX_PORT_MASK GENMASK(7, 0) 31 #define SOC_PINMUX_PIN_MASK GENMASK(15, 8) 32 #define SOC_PINMUX_HSIOM_MASK GENMASK(23, 16) 33 #define SOC_PINMUX_SIGNAL_MASK GENMASK(31, 24) 34 35 /* 36 * Pin flags/attributes 37 */ 38 #define SOC_GPIO_DEFAULT (0) 39 #define SOC_GPIO_FLAGS_POS (0) 40 #define SOC_GPIO_FLAGS_MASK GENMASK(6, 0) 41 #define SOC_GPIO_PULLUP_POS (0) 42 #define SOC_GPIO_PULLUP BIT(SOC_GPIO_PULLUP_POS) 43 #define SOC_GPIO_PULLDOWN_POS (1) 44 #define SOC_GPIO_PULLDOWN BIT(SOC_GPIO_PULLDOWN_POS) 45 #define SOC_GPIO_OPENDRAIN_POS (2) 46 #define SOC_GPIO_OPENDRAIN BIT(SOC_GPIO_OPENDRAIN_POS) 47 #define SOC_GPIO_OPENSOURCE_POS (3) 48 #define SOC_GPIO_OPENSOURCE BIT(SOC_GPIO_OPENSOURCE_POS) 49 50 /* Push-Pull means Strong, see dts/pinctrl/pincfg-node.yaml */ 51 #define SOC_GPIO_PUSHPULL_POS (4) 52 #define SOC_GPIO_PUSHPULL BIT(SOC_GPIO_PUSHPULL_POS) 53 54 /* Input-Enable means Input-Buffer, see dts/pinctrl/pincfg-node.yaml */ 55 #define SOC_GPIO_INPUTENABLE_POS (5) 56 #define SOC_GPIO_INPUTENABLE BIT(SOC_GPIO_INPUTENABLE_POS) 57 58 #define SOC_GPIO_HIGHZ_POS (6) 59 #define SOC_GPIO_HIGHZ BIT(SOC_GPIO_HIGHZ_POS) 60 61 /** Type for CAT1 Soc pin. */ 62 typedef struct { 63 /** 64 * Pinmux settings (port, pin and function). 65 * [0..7] - Port nunder 66 * [8..15] - Pin number 67 * [16..23]- HSIOM function 68 */ 69 uint32_t pinmux; 70 71 /** Pin configuration (bias, drive and slew rate). */ 72 uint32_t pincfg; 73 } pinctrl_soc_pin_t; 74 75 #define CAT1_PINMUX_GET_PORT_NUM(pinmux) FIELD_GET(SOC_PINMUX_PORT_MASK, pinmux) 76 #define CAT1_PINMUX_GET_PIN_NUM(pinmux) FIELD_GET(SOC_PINMUX_PIN_MASK, pinmux) 77 #define CAT1_PINMUX_GET_HSIOM_FUNC(pinmux) FIELD_GET(SOC_PINMUX_HSIOM_MASK, pinmux) 78 79 /** 80 * @brief Utility macro to initialize pinmux field in #pinctrl_pin_t. 81 * @param node_id Node identifier. 82 */ 83 #define Z_PINCTRL_CAT1_PINMUX_INIT(node_id) DT_PROP(node_id, pinmux) 84 85 /** 86 * @brief Utility macro to initialize pincfg field in #pinctrl_pin_t. 87 * @param node_id Node identifier. 88 */ 89 #define Z_PINCTRL_CAT1_PINCFG_INIT(node_id) ( \ 90 (DT_PROP(node_id, bias_pull_up) << SOC_GPIO_PULLUP_POS) | \ 91 (DT_PROP(node_id, bias_pull_down) << SOC_GPIO_PULLDOWN_POS) | \ 92 (DT_PROP(node_id, drive_open_drain) << SOC_GPIO_OPENDRAIN_POS) | \ 93 (DT_PROP(node_id, drive_open_source) << SOC_GPIO_OPENSOURCE_POS) | \ 94 (DT_PROP(node_id, drive_push_pull) << SOC_GPIO_PUSHPULL_POS) | \ 95 (DT_PROP(node_id, input_enable) << SOC_GPIO_INPUTENABLE_POS) | \ 96 (DT_PROP(node_id, bias_high_impedance) << SOC_GPIO_HIGHZ_POS)) 97 98 /** 99 * @brief Utility macro to initialize each pin. 100 * 101 * @param node_id Node identifier. 102 * @param state_prop State property name. 103 * @param idx State property entry index. 104 */ 105 #define Z_PINCTRL_STATE_PIN_INIT(node_id, state_prop, idx) \ 106 { .pinmux = Z_PINCTRL_CAT1_PINMUX_INIT( \ 107 DT_PROP_BY_IDX(node_id, state_prop, idx)), \ 108 .pincfg = Z_PINCTRL_CAT1_PINCFG_INIT( \ 109 DT_PROP_BY_IDX(node_id, state_prop, idx)) }, 110 111 /** 112 * @brief Utility macro to initialize state pins contained in a given property. 113 * 114 * @param node_id Node identifier. 115 * @param prop Property name describing state pins. 116 */ 117 #define Z_PINCTRL_STATE_PINS_INIT(node_id, prop) \ 118 { DT_FOREACH_PROP_ELEM(node_id, prop, Z_PINCTRL_STATE_PIN_INIT) } 119 120 /** @endcond */ 121 122 #ifdef __cplusplus 123 } 124 #endif 125 126 #endif /* ZEPHYR_SOC_ARM_INFINEON_CAT1_COMMON_PINCTRL_SOC_H_ */ 127
