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Searched +full:periph +full:- +full:32 +full:k +full:- +full:src (Results 1 – 10 of 10) sorted by relevance

/Zephyr-latest/samples/boards/microchip/mec15xxevb_assy6853/power_management/
Dmec15xxevb_assy6853.overlay4 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/clock/mchp_xec_pcr.h>
13 pll-32k-src = <MCHP_XEC_PLL_CLK32K_SRC_SIL_OSC>;
14 periph-32k-src = <MCHP_XEC_PERIPH_CLK32K_SRC_SO_SO>;
16 /* debug only, not using 32KHZ_IN pin */
17 pinctrl-0 = <&tst_clk_out_gpio060>;
19 pinctrl-names = "default";
/Zephyr-latest/samples/drivers/clock_control_xec/boards/
Dmec1501modular_assy6885.overlay4 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/clock/mchp_xec_pcr.h>
13 pll-32k-src = <MCHP_XEC_PLL_CLK32K_SRC_SIL_OSC>;
14 periph-32k-src = <MCHP_XEC_PERIPH_CLK32K_SRC_SO_SO>;
15 xtal-single-ended;
16 internal-osc-disable;
18 /* debug only, not using 32KHZ_IN pin */
19 pinctrl-0 = <&tst_clk_out_gpio060 &clk_32khz_out_gpio221>;
21 /* 32KHZ_IN is a clock source and no debug */
22 /* pinctrl-0 = <&clk_32khz_in_gpio165>; */
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Dmec15xxevb_assy6853.overlay4 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/clock/mchp_xec_pcr.h>
13 pll-32k-src = <MCHP_XEC_PLL_CLK32K_SRC_SIL_OSC>;
14 periph-32k-src = <MCHP_XEC_PERIPH_CLK32K_SRC_SO_SO>;
15 xtal-single-ended;
16 internal-osc-disable;
18 /* debug only, not using 32KHZ_IN pin */
19 pinctrl-0 = <&tst_clk_out_gpio060 &clk_32khz_out_gpio221>;
21 /* 32KHZ_IN is a clock source and no debug */
22 /* pinctrl-0 = <&clk_32khz_in_gpio165>; */
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Dmec172xevb_assy6906.overlay4 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/clock/mchp_xec_pcr.h>
13 pll-32k-src = <MCHP_XEC_PLL_CLK32K_SRC_SIL_OSC>;
14 periph-32k-src = <MCHP_XEC_PERIPH_CLK32K_SRC_SO_SO>;
15 xtal-single-ended;
16 internal-osc-disable;
18 /* debug only, not using 32KHZ_IN pin */
19 pinctrl-0 = <&tst_clk_out_gpio060 &clk_32khz_out_gpio221>;
21 /* 32KHZ_IN is a clock source and no debug */
22 /* pinctrl-0 = <&clk_32khz_in_gpio165>; */
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/Zephyr-latest/dts/bindings/clock/
Dmicrochip,xec-pcr.yaml2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "microchip,xec-pcr"
8 include: [clock-controller.yaml, pinctrl-device.yaml, base.yaml]
14 core-clock-div:
17 description: Divide 96 MHz PLL clock to produce Cortex-M4 core clock
19 slow-clock-div:
25 pll-32k-src:
28 description: 32 KHz clock source for PLL
30 periph-32k-src:
33 description: 32 KHz clock source for peripherals
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/Zephyr-latest/dts/arm/microchip/
Dmec1501hsz.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 #include <arm/armv7-m.dtsi>
8 #include <zephyr/dt-bindings/adc/adc.h>
9 #include <zephyr/dt-bindings/clock/mchp_xec_pcr.h>
10 #include <zephyr/dt-bindings/i2c/i2c.h>
11 #include <zephyr/dt-bindings/gpio/gpio.h>
12 #include <zephyr/dt-bindings/gpio/microchip-xec-gpio.h>
16 #address-cells = <1>;
17 #size-cells = <0>;
21 compatible = "arm,cortex-m4";
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Dmec172x_common.dtsi4 * SPDX-License-Identifier: Apache-2.0
11 compatible = "microchip,xec-pcr";
13 reg-names = "pcrr", "vbatr";
15 core-clock-div = <1>;
17 pll-32k-src = <MCHP_XEC_PLL_CLK32K_SRC_SIL_OSC>;
18 periph-32k-src = <MCHP_XEC_PERIPH_CLK32K_SRC_SO_SO>;
19 clk32kmon-period-min = <1435>;
20 clk32kmon-period-max = <1495>;
21 clk32kmon-duty-cycle-var-max = <132>;
22 clk32kmon-valid-min = <4>;
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/Zephyr-latest/samples/drivers/espi/src/
Dmain.c4 * SPDX-License-Identifier: Apache-2.0
249 return -1; in spi_saf_init()
395 return -1; in spi_saf_init()
427 limit = pr->start + pr->size - 1U; in pr_check_range()
430 if (regs->SAF_PROT_RG[pr->pr_num].START != (pr->start >> 12)) { in pr_check_range()
431 return -1; in pr_check_range()
434 if (regs->SAF_PROT_RG[pr->pr_num].LIMIT != (limit >> 12)) { in pr_check_range()
435 return -1; in pr_check_range()
443 if (pr->flags & MCHP_SAF_PR_FLAG_ENABLE) { in pr_check_enable()
444 if (regs->SAF_PROT_RG[pr->pr_num].LIMIT > regs->SAF_PROT_RG[pr->pr_num].START) { in pr_check_enable()
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/Zephyr-latest/doc/releases/
Drelease-notes-3.2.rst13 * Added support for :ref:`bin-blobs` (also see :ref:`west-blobs`).
15 * Converted all supported boards from ``pinmux`` to :ref:`pinctrl-guide`.
31 * CVE-2022-2993: Under embargo until 2022-11-03
33 * CVE-2022-2741: Under embargo until 2022-10-14
56 This definition can be used by third-party code to compile code conditional
58 Therefore, any third-party code integrated using the Zephyr build system will
91 changed from ``-ENETDOWN`` to ``-ENETUNREACH``. A return value of ``-ENETDOWN`` now indicates
129 * Removed support for configuring the CAN-FD maximum DLC value via Kconfig
156 valid for specific bindings to specify like :dtcompatible:`gpio-leds` and
157 :dtcompatible:`fixed-partitions`.
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Drelease-notes-3.3.rst14 * Introduced :ref:`USB-C <usbc_api>` device stack with PD (power delivery)
17 CMSIS-DSP as the default backend.
30 * CVE-2023-0359: Under embargo until 2023-04-20
32 * CVE-2023-0779: Under embargo until 2023-04-22
66 removed in favor of new :dtcompatible:`zephyr,flash-disk` devicetree binding.
71 * Starting from this release ``zephyr-`` prefixed tags won't be created
82 image states). Use of a truncated hash or non-sha256 hash will still work
88 registration function at boot-up. If applications register this then
93 application code, these will now automatically be registered at boot-up (this
129 This may cause out-of-tree scripts or commands to fail if they have relied
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