| /Zephyr-latest/samples/drivers/clock_control_litex/ |
| D | README.rst | 11 …lock Manager (MMCM) module to generate up to 7 clocks with defined phase, frequency and duty cycle.
41 …k1`` with default frequency set to 100MHz, 0 degrees phase offset and 50% duty cycle. Special care…
51 | This code will try to set on ``clk0`` frequency 50MHz, 90 degrees of phase offset and 75% duty cy…
60 .duty = 75,
70 Clock output status (frequency, duty and phase offset) can be acquired with function ``clock_contro…
80 * Duty cycle range,
82 * Setting frequency, duty and phase at once, then check clock status and rate,
109 [00:00:00.280,000] <inf> CLK_CTRL_LITEX: CLKOUT0: set duty: 50%
112 [00:00:00.400,000] <inf> CLK_CTRL_LITEX: CLKOUT1: set duty: 50%
123 [00:00:00.590,000] <inf> CLK_CTRL_LITEX: CLKOUT0: set duty: 25%
[all …]
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| /Zephyr-latest/dts/bindings/clock/ |
| D | litex,clkout.yaml | 40 litex,clock-duty-num:
44 default duty cycle numerator value
46 litex,clock-duty-den:
50 default duty cycle denominator value
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| D | microchip,xec-pcr.yaml | 51 clk32kmon-duty-cycle-var-max:
55 Maximum duty cycle variation. Difference in units of 48HMz between
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| /Zephyr-latest/samples/drivers/clock_control_litex/src/ |
| D | main.c | 25 /* Values for duty test */
75 printf("CLKOUT%d: get_status: rate:%d phase:%d duty:%d\n", in litex_clk_test_getters()
76 i, setup.rate, setup.phase, setup.duty); in litex_clk_test_getters()
89 .duty = LITEX_TEST_SINGLE_DUTY_VAL, in litex_clk_test_single()
95 .duty = LITEX_TEST_SINGLE_DUTY_VAL2, in litex_clk_test_single()
121 .duty = LITEX_TEST_FREQUENCY_DUTY_VAL, in litex_clk_test_freq()
184 .duty = LITEX_TEST_PHASE_DUTY_VAL, in litex_clk_test_phase()
190 .duty = LITEX_TEST_PHASE_DUTY_VAL in litex_clk_test_phase()
226 .duty = 0 in litex_clk_test_duty()
232 .duty = 0 in litex_clk_test_duty()
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| /Zephyr-latest/include/zephyr/drivers/clock_control/ |
| D | clock_control_litex.h | 34 * @param duty Duty cycle of clock signal in percent
41 uint8_t duty; member
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| /Zephyr-latest/drivers/clock_control/ |
| D | clock_control_litex.c | 442 lcko->def.freq, lcko->def.duty.num, in litex_clk_print_params()
443 lcko->def.duty.den, lcko->def.phase); in litex_clk_print_params()
445 LOG_DBG("div: %u freq: %u duty: %u/%u phase: %d per_off: %u", in litex_clk_print_params()
447 lcko->ts_config.duty.num, lcko->ts_config.duty.den, in litex_clk_print_params()
450 LOG_DBG("div: %u freq: %u duty: %u/%u phase: %d per_off: %u", in litex_clk_print_params()
452 lcko->config.duty.num, lcko->config.duty.den, in litex_clk_print_params()
840 * Duty Cycle
843 /* Returns accurate duty ratio of given clkout*/
845 struct clk_duty *duty) in litex_clk_get_duty_cycle() argument
865 /* get duty 50% when divider is off or fractional is enabled */ in litex_clk_get_duty_cycle()
[all …]
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| D | clock_control_litex.h | 62 "Invalid default duty"); \
70 lcko->def.duty.num = CLKOUT_DUTY_NUM(N); \
71 lcko->def.duty.den = CLKOUT_DUTY_DEN(N); \
170 struct clk_duty duty; member
206 struct clk_duty duty; member
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| D | Kconfig.litex | 13 such as phase, duty cycle, frequency for up to 7
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| /Zephyr-latest/drivers/pwm/ |
| D | pwm_ite_it8801.c | 46 /* PWM duty cycle register */
90 uint8_t duty, mask; in pwm_it8801_set_cycles() local
103 /* Set PWM channel duty cycle */ in pwm_it8801_set_cycles()
105 duty = 0; in pwm_it8801_set_cycles()
107 duty = pulse_cycles * 256 / period_cycles - 1; in pwm_it8801_set_cycles()
109 LOG_DBG("IT8801 pwm duty cycles = %d", duty); in pwm_it8801_set_cycles()
111 ret = i2c_reg_write_byte_dt(&config->i2c_dev, config->reg_dcr, duty); in pwm_it8801_set_cycles()
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| D | pwm_intel_blinky.c | 44 uint32_t duty; in bk_intel_set_cycles() local
57 duty = (pulse_cycles * PWM_DUTY_MAX) / period_cycles; in bk_intel_set_cycles()
59 if (duty) { in bk_intel_set_cycles()
60 val = PWM_DUTY_MAX - duty; in bk_intel_set_cycles()
73 if (duty > PWM_DUTY_MAX) { in bk_intel_set_cycles()
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| D | Kconfig.it8xxx2 | 14 eight PWM channels each with 8-bit duty cycle.
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| D | pwm_mchp_xec_bbled.c | 45 /* BBLED PWM mode uses the duty cycle to set the PWM frequency:
54 * Duty cycle is derived from LIMITS register MINIMUM 8-bit field
61 * BBLED PWM mode duty cycle specified by 8-bit MIN field of the LIMITS register
138 * LIMITS.MIN = duty cycle = [1, 254]
203 * compute duty cycle = 256 * (pulse_cycles / period_cycles).
206 * program duty cycle info bits[7:0] of Limits register
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| /Zephyr-latest/dts/bindings/display/ |
| D | istech,ist3931.yaml | 49 duty-ratio:
52 description: Com_1~COM_N is select, N=Duty-ratio.
59 Frame frequency = Row frequency / Duty-ratio
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| /Zephyr-latest/dts/bindings/pwm/ |
| D | nxp,s32-emios-pwm.yaml | 22 duty-cycle = <32768>;
30 duty-cycle = <32768>;
39 duty-cycle = <32768>;
102 - OPWFMB: provides waveforms with variable duty cycle and frequency,
135 duty-cycle:
138 Duty-cycle (in ticks) for PWM channel at boot time.
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| D | infineon,xmc4xxx-ccu8-pwm.yaml | 63 signal can, for example, be used as PWM, but note that the duty cycle of the
64 low signal will be (1 - duty) as set via the API.
68 duty cycle and high/low dead times. But the pulse duration applies to
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| /Zephyr-latest/drivers/i2c/ |
| D | i2c_renesas_ra_iic.c | 58 uint32_t duty; member
335 result->duty = in calc_iic_master_bitrate()
343 (result->duty > requested_duty ? result->duty - requested_duty in calc_iic_master_bitrate()
344 : requested_duty - result->duty) / in calc_iic_master_bitrate()
348 " [output] bitrate[%u] duty[%u] divider[%u] brh[%u] brl[%u] " in calc_iic_master_bitrate()
350 __func__, total_brl_brh, brh, divider, result->bitrate, result->duty, in calc_iic_master_bitrate()
412 /* Calculate the actual bitrate and duty cycle. */ in calc_iic_master_clock_setting()
418 /* Adjust duty cycle down if it helps. */ in calc_iic_master_clock_setting()
421 while (test_bitrate.duty > requested_duty) { in calc_iic_master_clock_setting()
440 /* Adjust duty cycle up if it helps. */ in calc_iic_master_clock_setting()
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| D | i2c_lpc11u6x.h | 61 volatile uint32_t sclh; /* SCL Duty Cycle */
62 volatile uint32_t scll; /* SCL Duty Cycle */
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| /Zephyr-latest/dts/bindings/sensor/ |
| D | vishay,vcnl4040.yaml | 36 led-duty-cycle:
40 description: LED duty cycle in Hz
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| /Zephyr-latest/drivers/led/ |
| D | led_mchp_xec.c | 118 /* return duty cycle scaled to [0, 255]
129 * BBLED blinking mode uses an 8-bit accumulator and an 8-bit duty cycle
130 * register. The duty cycle register is programmed once and the
134 * 8-bit duty cycle values: 0x00 = full off, 0xff = full on.
138 * duty_cycle in [0, 1]. Register value for duty cycle is
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| /Zephyr-latest/samples/sensor/vcnl4040/boards/ |
| D | adafruit_feather_stm32f405.overlay | 13 led-duty-cycle = <320>;
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| /Zephyr-latest/dts/bindings/i2c/ |
| D | renesas,ra-iic.yaml | 29 duty-cycle-percent:
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| /Zephyr-latest/boards/nxp/mr_canhubk3/ |
| D | mr_canhubk3.dts | 517 duty-cycle = <0>;
526 duty-cycle = <0>;
535 duty-cycle = <0>;
544 duty-cycle = <0>;
553 duty-cycle = <0>;
562 duty-cycle = <0>;
570 duty-cycle = <0>;
609 duty-cycle = <0>;
617 duty-cycle = <0>;
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| /Zephyr-latest/drivers/led_strip/ |
| D | Kconfig.lpd880x | 16 duty cycle can be set at 7 bit resolution via a
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| /Zephyr-latest/tests/drivers/pwm/pwm_loopback/boards/ |
| D | mr_canhubk3.overlay | 36 /delete-property/ duty-cycle;
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| /Zephyr-latest/samples/sensor/sgp40_sht4x/ |
| D | Kconfig | 17 Maximum duty cycle for using the heater is 5%
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