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/Zephyr-latest/tests/drivers/uart/uart_async_api/boards/
Dnucleo_f767zi.overlay4 dmas = <&dma2 7 5 0x28440 0x03>,
5 <&dma2 2 5 0x28480 0x03>;
9 &dma2 {
Ddisco_l475_iot1.overlay4 dmas = <&dma2 3 2 (STM32_DMA_PERIPH_TX | STM32_DMA_PRIORITY_HIGH)>,
5 <&dma2 5 2 (STM32_DMA_PERIPH_RX | STM32_DMA_PRIORITY_HIGH)>;
9 &dma2 {
Dnucleo_f429zi.overlay4 dmas = <&dma2 7 5 0x28440 0x03>,
5 <&dma2 2 5 0x28480 0x03>;
9 &dma2 {
Dnucleo_f746zg.overlay4 dmas = <&dma2 7 5 0x28440 0x03>,
5 <&dma2 2 5 0x28480 0x03>;
10 &dma2 {
Dnucleo_f207zg.overlay4 dmas = <&dma2 7 5 0x28440 0x03>,
5 <&dma2 2 5 0x28480 0x03>;
/Zephyr-latest/samples/subsys/fs/fs_sample/boards/
Dstm32f746g_disco_dma.overlay8 dmas = <&dma2 6 4 0x30000 0x00>, <&dma2 3 4 0x30000 0x00>;
12 &dma2 {
/Zephyr-latest/dts/arm/st/f4/
Dstm32f411.dtsi38 dmas = <&dma2 3 3 0x400 0x3
39 &dma2 2 3 0x400 0x3>;
51 dmas = <&dma2 1 4 0x400 0x3
52 &dma2 0 4 0x400 0x3>;
64 dmas = <&dma2 6 7 0x400 0x3
65 &dma2 5 7 0x400 0x3>;
Dstm32f410.dtsi45 dmas = <&dma2 3 3 0x400 0x3
46 &dma2 2 3 0x400 0x3>;
71 dmas = <&dma2 6 7 0x400 0x3
72 &dma2 5 7 0x400 0x3>;
/Zephyr-latest/tests/drivers/spi/spi_loopback/boards/
Dnucleo_f207zg.overlay8 dmas = <&dma2 5 3 0x28440 0x03
9 &dma2 2 3 0x28480 0x03>;
27 &dma2 {
Dnucleo_f411re.overlay8 dmas = <&dma2 5 3 0x28440 0x03
9 &dma2 2 3 0x28480 0x03>;
27 &dma2 {
Dnucleo_f429zi.overlay8 dmas = <&dma2 5 3 0x28440 0x03
9 &dma2 2 3 0x28480 0x03>;
27 &dma2 {
Dnucleo_f746zg.overlay9 dmas = <&dma2 5 3 0x28440 0x03
10 &dma2 2 3 0x28480 0x03>;
24 &dma2 {
Dnucleo_f767zi.overlay9 dmas = <&dma2 5 3 0x28440 0x03
10 &dma2 2 3 0x28480 0x03>;
24 &dma2 {
/Zephyr-latest/dts/bindings/qspi/
Dst,stm32-qspi.yaml49 /* select DMA2 channel 7 request 3 for QUADSPI */
50 dmas = <&dma2 7 3 (STM32_DMA_PERIPH_TX | STM32_DMA_PRIORITY_HIGH)>;
52 /* select DMA2 channel 0, request 20 for QUADSPI */
53 dmas = <&dma2 0 20 (STM32_DMA_PERIPH_TX | STM32_DMA_PRIORITY_HIGH)>;
/Zephyr-latest/include/zephyr/devicetree/
Ddma.h33 * dma2: dma@... { ... };
37 * <&dma2 6 3 0x404 0x5>;
43 * DT_DMAS_CTLR_BY_IDX(DT_NODELABEL(n), 1) // DT_NODELABEL(dma2)
61 * dma2: dma@... { ... };
65 * <&dma2 6 3 0x404 0x5>;
72 * DT_DMAS_CTLR_BY_NAME(DT_NODELABEL(n), rx) // DT_NODELABEL(dma2)
136 * dma2: dma@... {
143 * <&dma2 6 0x404>;
189 * dma2: dma@... {
196 * <&dma2 6 0x404>;
/Zephyr-latest/tests/drivers/adc/adc_api/boards/
Dnucleo_f746zg.overlay15 dmas = <&dma2 0 0 (STM32_DMA_PERIPH_RX | STM32_DMA_MEM_16BITS |
40 &dma2 {
Dnucleo_f207zg.overlay15 dmas = <&dma2 0 0 (STM32_DMA_PERIPH_RX | STM32_DMA_MEM_16BITS |
40 &dma2 {
Dnucleo_f401re.overlay15 dmas = <&dma2 0 0 (STM32_DMA_PERIPH_RX | STM32_DMA_MEM_16BITS |
40 &dma2 {
Dnucleo_f429zi.overlay15 dmas = <&dma2 0 0 (STM32_DMA_PERIPH_RX | STM32_DMA_MEM_16BITS |
40 &dma2 {
/Zephyr-latest/dts/bindings/dma/
Dst,stm32-dma-v1.yaml60 dma2: dma-controller@40020400 {
68 For the client part, example for stm32f411 on DMA2 instance
72 dmas = <&dma2 5 3 STM32_DMA_PERIPH_TX STM32_DMA_FIFO_FULL>,
73 <&dma2 2 3 STM32_DMA_PERIPH_RX STM32_DMA_FIFO_FULL>;
/Zephyr-latest/dts/bindings/mmc/
Dst,stm32-sdmmc.yaml66 dmas = <&dma2 4 6 0x30000 0x00>, <&dma2 4 3 0x30000 0x00>;
/Zephyr-latest/tests/drivers/dma/chan_blen_transfer/boards/
Dnucleo_f429zi.overlay7 tst_dma0: &dma2 { };
Dnucleo_l476rg.overlay11 &dma2 {
Dstm32mp157c_dk2.overlay9 &dma2 {
/Zephyr-latest/tests/drivers/dma/loop_transfer/boards/
Dnucleo_f429zi.overlay7 tst_dma0: &dma2 { };

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