Searched full:divides (Results 1 – 17 of 17) sorted by relevance
| /Zephyr-latest/dts/bindings/clock/ |
| D | nxp,imx-ccm-fnpll.yaml | 20 Loop divider. Divides PLL feedback loop (effectively multiplying output
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| /Zephyr-latest/dts/bindings/can/ |
| D | st,stm32-fdcan.yaml | 41 Divides the kernel clock giving the time quanta clock that is fed to the
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| D | st,stm32h7-fdcan.yaml | 40 Divides the kernel clock giving the time quanta clock that is fed to the FDCAN core
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| /Zephyr-latest/dts/bindings/timer/ |
| D | adi,max32-timer.yaml | 52 The prescaler that divides the timers source clock to set the timers count clock as follows:
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| /Zephyr-latest/dts/bindings/adc/ |
| D | adi,max32-adc.yaml | 60 The clock divider divides the ADC source clock to set the ADC clock frequency as follows:
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| /Zephyr-latest/drivers/clock_control/ |
| D | clock_control_wch_rcc.c | 71 /* The range 0b1000 divides by a power of 2, where 0b1000 is /2, 0b1001 is /4, etc. in clock_control_wch_rcc_get_rate()
75 /* The range 0b0nnn divides by n + 1, where 0b0000 is /1, 0b001 is /2, etc. */ in clock_control_wch_rcc_get_rate()
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| D | clock_control_mchp_xec.c | 747 * Programming the PCR clock divider that divides the clock input to the ARM
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| /Zephyr-latest/dts/bindings/pwm/ |
| D | infineon,xmc4xxx-ccu4-pwm.yaml | 15 prescalar which divides the clock.
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| D | infineon,xmc4xxx-ccu8-pwm.yaml | 26 slice has a dead time prescaler, which divides the slice clock
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| /Zephyr-latest/samples/drivers/led/pwm/boards/ |
| D | mec15xxevb_assy6853.overlay | 14 * BBLED hardware divides input clock (32KHz or 48MHz) by (256 * (prescalar+1)
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| D | mec172xevb_assy6906.overlay | 16 * BBLED hardware divides input clock (32KHz or 48MHz) by (256 * (prescalar+1)
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| /Zephyr-latest/tests/kernel/sched/schedule_api/src/ |
| D | test_sched_timeslice_reset.c | 141 * value divides properly. in ZTEST()
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| /Zephyr-latest/drivers/spi/ |
| D | spi_opentitan.c | 109 * Applied divider (divides f_in / 2) is CLKDIV register (16 bit) + 1. in spi_config()
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| /Zephyr-latest/soc/microchip/mec/mec172x/reg/ |
| D | mec172x_pcr.h | 105 * Divides 96MHz clock to ARM Cortex-M4 core including
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| /Zephyr-latest/doc/kernel/services/scheduling/ |
| D | index.rst | 172 The scheduler divides time into a series of **time slices**, where slices
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| /Zephyr-latest/doc/services/storage/zms/ |
| D | zms.rst | 12 ZMS divides the memory space into sectors (minimum 2), and each sector is filled with key-value
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| /Zephyr-latest/subsys/fs/ext2/ |
| D | ext2_impl.c | 218 LOG_ERR("expecting sector size that divides 1024 (got: %lld)", write_size); in ext2_init_storage()
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