Searched full:ch5 (Results 1 – 19 of 19) sorted by relevance
| /hal_espressif-latest/components/soc/esp32c6/include/soc/ |
| D | ledc_reg.h | 1832 * Ledc ch5 gamma ram write register.
1836 * Ledc ch5 gamma duty inc of current ram write address.This register is used to
1846 * Ledc ch5 gamma duty cycle of current ram write address.The duty will change every
1854 * Ledc ch5 gamma scale of current ram write address.This register is used to
1862 * Ledc ch5 gamma duty num of current ram write address.This register is used to
1871 * Ledc ch5 gamma ram write address register.
1875 * Ledc ch5 gamma ram write address.
1883 * Ledc ch5 gamma ram read address register.
1887 * Ledc ch5 gamma ram read address.
1895 * Ledc ch5 gamma ram read data register.
[all …]
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| D | ledc_struct.h | 102 * Ledc ch5 duty change end event enable register, write 1 to enable this event.
127 * Ledc ch5 overflow count pulse event enable register, write 1 to enable this event.
184 * Ledc ch5 duty scale update task enable register, write 1 to enable this task.
250 * Ledc ch5 signal out disable task enable register, write 1 to enable this task.
275 * Ledc ch5 overflow count reset task enable register, write 1 to enable this task.
341 * Ledc ch5 gamma restart task enable register, write 1 to enable this task.
366 * Ledc ch5 gamma pause task enable register, write 1 to enable this task.
391 * Ledc ch5 gamma resume task enable register, write 1 to enable this task.
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| D | soc_etm_struct.h | 40 * ch5 enable
177 * ch5 set
314 * ch5 clear
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| D | soc_etm_reg.h | 54 * ch5 enable
283 * ch5 set
512 * ch5 clear
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| D | efuse_struct.h | 766 * ADC1 init code at atten0 ch5
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| D | efuse_reg.h | 986 * ADC1 init code at atten0 ch5
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| /hal_espressif-latest/components/soc/esp32h2/include/soc/ |
| D | ledc_reg.h | 1832 * Ledc ch5 gamma ram write register.
1836 * Ledc ch5 gamma duty inc of current ram write address.This register is used to
1846 * Ledc ch5 gamma duty cycle of current ram write address.The duty will change every
1854 * Ledc ch5 gamma scale of current ram write address.This register is used to
1862 * Ledc ch5 gamma duty num of current ram write address.This register is used to
1871 * Ledc ch5 gamma ram write address register.
1875 * Ledc ch5 gamma ram write address.
1883 * Ledc ch5 gamma ram read address register.
1887 * Ledc ch5 gamma ram read address.
1895 * Ledc ch5 gamma ram read data register.
[all …]
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| D | ledc_struct.h | 102 * Ledc ch5 duty change end event enable register, write 1 to enable this event.
127 * Ledc ch5 overflow count pulse event enable register, write 1 to enable this event.
184 * Ledc ch5 duty scale update task enable register, write 1 to enable this task.
250 * Ledc ch5 signal out disable task enable register, write 1 to enable this task.
275 * Ledc ch5 overflow count reset task enable register, write 1 to enable this task.
341 * Ledc ch5 gamma restart task enable register, write 1 to enable this task.
366 * Ledc ch5 gamma pause task enable register, write 1 to enable this task.
391 * Ledc ch5 gamma resume task enable register, write 1 to enable this task.
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| D | soc_etm_struct.h | 40 * ch5 enable
177 * ch5 set
314 * ch5 clear
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| D | soc_etm_reg.h | 54 * ch5 enable
283 * ch5 set
512 * ch5 clear
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| /hal_espressif-latest/zephyr/port/pincfgs/ |
| D | esp32c2.yml | 89 ch5:
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| D | esp32c3.yml | 141 ch5:
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| D | esp32c6.yml | 94 ch5:
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| D | esp32s2.yml | 174 ch5:
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| D | esp32.yml | 201 ch5:
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| D | esp32s3.yml | 200 ch5:
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| /hal_espressif-latest/components/efuse/esp32c6/ |
| D | esp_efuse_table.csv | 191 …1_INIT_CODE_ATTEN0_CH5, EFUSE_BLK2, 245, 4, [] ADC1 init code at atten0 ch5
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| D | esp_efuse_table.c | 709 {EFUSE_BLK2, 245, 4}, // [] ADC1 init code at atten0 ch5,
1618 &ADC1_INIT_CODE_ATTEN0_CH5[0], // [] ADC1 init code at atten0 ch5
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| /hal_espressif-latest/tools/esptool_py/espefuse/efuse_defs/ |
| D | esp32c6.yaml | 99 … : '', dict : '', desc: ADC1 init code at atten0 ch5, rloc: 'EFUSE_RD_SY…
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