Searched full:ch3 (Results 1 – 20 of 20) sorted by relevance
| /hal_espressif-latest/components/soc/esp32c6/include/soc/ |
| D | ledc_reg.h | 1682 * Ledc ch3 gamma ram write register.
1686 * Ledc ch3 gamma duty inc of current ram write address.This register is used to
1696 * Ledc ch3 gamma duty cycle of current ram write address.The duty will change every
1704 * Ledc ch3 gamma scale of current ram write address.This register is used to
1712 * Ledc ch3 gamma duty num of current ram write address.This register is used to
1721 * Ledc ch3 gamma ram write address register.
1725 * Ledc ch3 gamma ram write address.
1733 * Ledc ch3 gamma ram read address register.
1737 * Ledc ch3 gamma ram read address.
1745 * Ledc ch3 gamma ram read data register.
[all …]
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| D | ledc_struct.h | 94 * Ledc ch3 duty change end event enable register, write 1 to enable this event.
119 * Ledc ch3 overflow count pulse event enable register, write 1 to enable this event.
176 * Ledc ch3 duty scale update task enable register, write 1 to enable this task.
242 * Ledc ch3 signal out disable task enable register, write 1 to enable this task.
267 * Ledc ch3 overflow count reset task enable register, write 1 to enable this task.
333 * Ledc ch3 gamma restart task enable register, write 1 to enable this task.
358 * Ledc ch3 gamma pause task enable register, write 1 to enable this task.
383 * Ledc ch3 gamma resume task enable register, write 1 to enable this task.
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| D | soc_etm_struct.h | 32 * ch3 enable
169 * ch3 set
306 * ch3 clear
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| D | soc_etm_reg.h | 40 * ch3 enable
269 * ch3 set
498 * ch3 clear
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| D | efuse_struct.h | 758 * ADC1 init code at atten0 ch3
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| D | efuse_reg.h | 972 * ADC1 init code at atten0 ch3
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| /hal_espressif-latest/components/soc/esp32h2/include/soc/ |
| D | ledc_reg.h | 1682 * Ledc ch3 gamma ram write register.
1686 * Ledc ch3 gamma duty inc of current ram write address.This register is used to
1696 * Ledc ch3 gamma duty cycle of current ram write address.The duty will change every
1704 * Ledc ch3 gamma scale of current ram write address.This register is used to
1712 * Ledc ch3 gamma duty num of current ram write address.This register is used to
1721 * Ledc ch3 gamma ram write address register.
1725 * Ledc ch3 gamma ram write address.
1733 * Ledc ch3 gamma ram read address register.
1737 * Ledc ch3 gamma ram read address.
1745 * Ledc ch3 gamma ram read data register.
[all …]
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| D | ledc_struct.h | 94 * Ledc ch3 duty change end event enable register, write 1 to enable this event.
119 * Ledc ch3 overflow count pulse event enable register, write 1 to enable this event.
176 * Ledc ch3 duty scale update task enable register, write 1 to enable this task.
242 * Ledc ch3 signal out disable task enable register, write 1 to enable this task.
267 * Ledc ch3 overflow count reset task enable register, write 1 to enable this task.
333 * Ledc ch3 gamma restart task enable register, write 1 to enable this task.
358 * Ledc ch3 gamma pause task enable register, write 1 to enable this task.
383 * Ledc ch3 gamma resume task enable register, write 1 to enable this task.
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| D | soc_etm_struct.h | 32 * ch3 enable
169 * ch3 set
306 * ch3 clear
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| D | soc_etm_reg.h | 40 * ch3 enable
269 * ch3 set
498 * ch3 clear
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| /hal_espressif-latest/zephyr/port/pincfgs/ |
| D | esp32c2.yml | 83 ch3:
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| D | esp32c3.yml | 135 ch3:
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| D | esp32c6.yml | 88 ch3:
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| D | esp32s2.yml | 168 ch3:
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| D | esp32.yml | 195 ch3:
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| D | esp32s3.yml | 194 ch3:
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| /hal_espressif-latest/components/soc/esp32c3/include/soc/ |
| D | rmt_struct.h | 234 uint32_t ch3: 1; member
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| /hal_espressif-latest/components/efuse/esp32c6/ |
| D | esp_efuse_table.csv | 189 …1_INIT_CODE_ATTEN0_CH3, EFUSE_BLK2, 237, 4, [] ADC1 init code at atten0 ch3
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| D | esp_efuse_table.c | 701 {EFUSE_BLK2, 237, 4}, // [] ADC1 init code at atten0 ch3,
1608 &ADC1_INIT_CODE_ATTEN0_CH3[0], // [] ADC1 init code at atten0 ch3
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| /hal_espressif-latest/tools/esptool_py/espefuse/efuse_defs/ |
| D | esp32c6.yaml | 97 … : '', dict : '', desc: ADC1 init code at atten0 ch3, rloc: 'EFUSE_RD_SY…
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