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/Zephyr-latest/dts/bindings/clock/
Dst,stm32-rcc.yaml2 # SPDX-License-Identifier: Apache-2.0
7 clocks for AHB (Advanced High Performance) and APB (Advanced Peripheral) bus domains.
13 Core clock frequency should also be defined, using "clock-frequency" property.
15 Core clock frequency = SYSCLK / AHB prescaler
17 prescaler properties.
21 ahb-prescaler = <2>;
22 clock-frequency = <DT_FREQ_M(40)>; /* = SYSCLK / AHB prescaler */
23 apb1-prescaler = <1>;
24 apb2-prescaler = <1>;
81 compatible: "st,stm32-rcc"
[all …]
Dst,stm32wba-rcc.yaml2 # SPDX-License-Identifier: Apache-2.0
7 clocks for AHB (Advanced High Performance) and APB (Advanced Peripheral) bus domains.
13 Core clock frequency should also be defined, using "clock-frequency" property.
15 Core clock frequency = SYSCLK / AHB prescaler
17 matching prescaler properties.
21 ahb-prescaler = <2>;
22 clock-frequency = <DT_FREQ_M(40)>; /* = SYSCLK / AHB prescaler */
23 apb1-presacler = <1>;
24 apb2-presacler = <1>;
25 apb7-presacler = <7>;
[all …]
Dst,stm32f3-rcc.yaml2 # SPDX-License-Identifier: Apache-2.0
6 Adds the STM32F3 ADC prescaler to the standard generic STM32 RCC.
7 For more description confere st,stm32-rcc.yaml
9 compatible: "st,stm32f3-rcc"
11 include: st,stm32-rcc.yaml
14 adc12-prescaler:
17 - 0 # Synchronous mode
18 - 1 # not divided
19 - 2
20 - 4
[all …]
Dst,stm32mp1-rcc.yaml2 # SPDX-License-Identifier: Apache-2.0
8 clock-frequency (mlhclk_ck).
10 compatible: "st,stm32mp1-rcc"
13 - name: st,stm32-rcc.yaml
14 property-blocklist:
15 - ahb-prescaler
16 - apb1-prescaler
17 - apb2-prescaler
18 - undershoot-prevention
/Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_core/boards/
Df2_f4_f7_pll_100_hsi_16_ahb_2.overlay4 * SPDX-License-Identifier: Apache-2.0
17 div-m = <8>;
18 mul-n = <200>;
19 div-p = <4>;
26 ahb-prescaler = <2>;
27 clock-frequency = <DT_FREQ_M(50)>; /* Pll Output (100) / AHB prescaler */
28 apb1-prescaler = <2>;
29 apb2-prescaler = <2>;
/Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32u5_core/boards/
Dpll_msis_ahb_2_40.overlay4 * SPDX-License-Identifier: Apache-2.0
18 msi-range = <4>;
19 msi-pll-mode;
23 div-m = <1>;
24 mul-n = <80>;
25 div-q = <4>;
26 div-r = <4>;
33 ahb-prescaler = <2>; /* Use AHB prescaler to reduce HCLK */
34 clock-frequency = <DT_FREQ_M(40)>;
35 apb1-prescaler = <1>;
[all …]
Dhsi_16.overlay4 * SPDX-License-Identifier: Apache-2.0
18 clock-frequency = <DT_FREQ_M(16)>;
19 ahb-prescaler = <1>;
20 apb1-prescaler = <1>;
21 apb2-prescaler = <1>;
22 apb3-prescaler = <1>;
Dmsis_24.overlay4 * SPDX-License-Identifier: Apache-2.0
18 msi-range = <1>;
19 msi-pll-mode;
24 clock-frequency = <DT_FREQ_M(24)>;
25 ahb-prescaler = <1>;
26 apb1-prescaler = <1>;
27 apb2-prescaler = <1>;
28 apb3-prescaler = <1>;
Dmsis_48.overlay4 * SPDX-License-Identifier: Apache-2.0
18 msi-range = <0>;
19 msi-pll-mode;
24 clock-frequency = <DT_FREQ_M(48)>;
25 ahb-prescaler = <1>;
26 apb1-prescaler = <1>;
27 apb2-prescaler = <1>;
28 apb3-prescaler = <1>;
Dpll_hsi_160.overlay4 * SPDX-License-Identifier: Apache-2.0
17 div-m = <4>;
18 mul-n = <40>;
19 div-q = <2>;
20 div-r = <1>;
27 clock-frequency = <DT_FREQ_M(160)>;
28 ahb-prescaler = <1>;
29 apb1-prescaler = <1>;
30 apb2-prescaler = <1>;
31 apb3-prescaler = <1>;
Dpll_hsi_40.overlay4 * SPDX-License-Identifier: Apache-2.0
17 div-m = <4>;
18 mul-n = <10>;
19 div-q = <2>;
20 div-r = <1>;
27 clock-frequency = <DT_FREQ_M(40)>;
28 ahb-prescaler = <1>;
29 apb1-prescaler = <1>;
30 apb2-prescaler = <1>;
31 apb3-prescaler = <1>;
Dhse_16.overlay4 * SPDX-License-Identifier: Apache-2.0
19 clock-frequency = <DT_FREQ_M(16)>;
20 hse-bypass;
25 clock-frequency = <DT_FREQ_M(16)>;
26 ahb-prescaler = <1>;
27 apb1-prescaler = <1>;
28 apb2-prescaler = <1>;
29 apb3-prescaler = <1>;
/Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32h5_core/boards/
Dpll_csi_ahb_2_100.overlay5 * SPDX-License-Identifier: Apache-2.0
18 div-m = <1>;
19 mul-n = <100>;
20 div-p = <2>;
21 div-q = <2>;
22 div-r = <2>;
29 ahb-prescaler = <2>; /* Use AHB prescaler to reduce HCLK */
30 clock-frequency = <DT_FREQ_M(100)>;
31 apb1-prescaler = <1>;
32 apb2-prescaler = <1>;
[all …]
Dpll_hse24_ahb_2_100.overlay5 * SPDX-License-Identifier: Apache-2.0
14 clock-frequency = <DT_FREQ_M(24)>;
19 div-m = <6>;
20 mul-n = <100>;
21 div-p = <2>;
22 div-q = <2>;
23 div-r = <2>;
30 ahb-prescaler = <2>; /* Use AHB prescaler to reduce HCLK */
31 clock-frequency = <DT_FREQ_M(100)>;
32 apb1-prescaler = <1>;
[all …]
Dpll_hse25_ahb_2_100.overlay5 * SPDX-License-Identifier: Apache-2.0
14 hse-bypass; /* X3 is a 25MHz oscillator on PH0 */
15 clock-frequency = <DT_FREQ_M(25)>;
20 div-m = <4>;
21 mul-n = <64>;
22 div-p = <2>;
23 div-q = <2>;
24 div-r = <2>;
31 ahb-prescaler = <2>; /* Use AHB prescaler to reduce HCLK */
32 clock-frequency = <DT_FREQ_M(100)>;
[all …]
Dcsi4.overlay5 * SPDX-License-Identifier: Apache-2.0
19 clock-frequency = <DT_FREQ_M(4)>;
20 ahb-prescaler = <1>;
21 apb1-prescaler = <1>;
22 apb2-prescaler = <1>;
23 apb3-prescaler = <1>;
Dhse24.overlay5 * SPDX-License-Identifier: Apache-2.0
20 clock-frequency = <DT_FREQ_M(24)>;
25 clock-frequency = <DT_FREQ_M(24)>;
26 ahb-prescaler = <1>;
27 apb1-prescaler = <1>;
28 apb2-prescaler = <1>;
29 apb3-prescaler = <1>;
/Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32wba_core/boards/
Dclear_clocks.overlay4 * SPDX-License-Identifier: Apache-2.0
14 /delete-property/ hse-div2;
22 /delete-property/ div-m;
23 /delete-property/ mul-n;
24 /delete-property/ div-q;
25 /delete-property/ div-r;
26 /delete-property/ clocks;
31 /delete-property/ clocks;
32 /delete-property/ clock-frequency;
33 /delete-property/ ahb-prescaler;
[all …]
Dhse_32.overlay4 * SPDX-License-Identifier: Apache-2.0
18 clock-frequency = <DT_FREQ_M(32)>;
19 ahb-prescaler = <1>;
20 ahb5-prescaler = <1>;
21 apb1-prescaler = <1>;
22 apb2-prescaler = <1>;
23 apb7-prescaler = <1>;
Dhse_16.overlay4 * SPDX-License-Identifier: Apache-2.0
14 hse-div2;
19 clock-frequency = <DT_FREQ_M(16)>;
20 ahb-prescaler = <1>;
21 apb1-prescaler = <1>;
22 apb2-prescaler = <1>;
23 apb7-prescaler = <1>;
Dhsi_16_ahb5_div.overlay4 * SPDX-License-Identifier: Apache-2.0
18 clock-frequency = <DT_FREQ_M(16)>;
19 ahb-prescaler = <1>;
20 ahb5-div;
21 apb1-prescaler = <1>;
22 apb2-prescaler = <1>;
23 apb7-prescaler = <1>;
Dhsi_16.overlay4 * SPDX-License-Identifier: Apache-2.0
18 clock-frequency = <DT_FREQ_M(16)>;
19 ahb-prescaler = <1>;
20 apb1-prescaler = <1>;
21 apb2-prescaler = <1>;
22 apb7-prescaler = <1>;
Dpll_hse_100.overlay4 * SPDX-License-Identifier: Apache-2.0
14 clock-frequency = <DT_FREQ_M(32)>;
18 div-m = <8>;
19 mul-n = <100>;
20 div-q = <2>;
21 div-r = <4>;
28 clock-frequency = <DT_FREQ_M(100)>;
29 ahb-prescaler = <1>;
30 ahb5-prescaler = <4>;
31 apb1-prescaler = <1>;
[all …]
Dpll_hse_100_ahb_50.overlay4 * SPDX-License-Identifier: Apache-2.0
14 clock-frequency = <DT_FREQ_M(32)>;
18 div-m = <8>;
19 mul-n = <100>;
20 div-q = <2>;
21 div-r = <4>;
28 ahb-prescaler = <2>;
29 clock-frequency = <DT_FREQ_M(50)>;
30 ahb5-prescaler = <4>;
31 apb1-prescaler = <1>;
[all …]
/Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32u5_devices/boards/
Dcore_init.overlay4 * SPDX-License-Identifier: Apache-2.0
19 /delete-property/ clock-frequency;
20 /delete-property/ hse-bypass;
33 /delete-property/ msi-range;
34 /delete-property/ msi-pll-mode;
39 /delete-property/ msi-range;
40 /delete-property/ msi-pll-mode;
44 /delete-property/ div-m;
45 /delete-property/ mul-n;
46 /delete-property/ div-q;
[all …]

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