Searched full:sysclock (Results 1 – 6 of 6) sorted by relevance
97 Only required when SysClock source is PLL1.133 AHB5 divider. Applies only when SysClock source is HSI16 or HSE32.134 When enabled, AHB5 clock is SysClock / 2.135 When disabled, SysClock is not divided.
31 # If sysclock is not LPTIM, tick of 10000 is too high for a frequency lower than 32MHz
581 /* Make sure that selected sysclock is enabled */ in smartbond_clocks_init()
550 /* If required, apply max step freq for Sysclock w/ PLL input */ in stm32_clock_control_init()
436 * Enable the Booster mode before enabling then PLL for sysclock above 55MHz
287 /* After sysclock is configured, tweak the voltage scale down */
