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Searched full:stm32_src_pll1_p (Results 1 – 10 of 10) sorted by relevance

/Zephyr-latest/dts/bindings/phy/
Dst,stm32u5-otghs-phy.yaml32 <&rcc STM32_SRC_PLL1_P OTGHS_SEL(1)>;
36 <&rcc (STM32_SRC_PLL1_P | STM32_CLOCK_DIV(2)) OTGHS_SEL(3)>;
/Zephyr-latest/include/zephyr/dt-bindings/clock/
Dstm32wba_clock.h28 #define STM32_SRC_PLL1_P (STM32_SRC_PCLK7 + 1) macro
29 #define STM32_SRC_PLL1_Q (STM32_SRC_PLL1_P + 1)
32 #define STM32_SRC_CLOCK_MIN STM32_SRC_PLL1_P
Dstm32h7rs_clock.h25 #define STM32_SRC_PLL1_P (STM32_SRC_CSI_KER + 1) macro
26 #define STM32_SRC_PLL1_Q (STM32_SRC_PLL1_P + 1)
Dstm32h7_clock.h25 #define STM32_SRC_PLL1_P (STM32_SRC_CSI_KER + 1) macro
26 #define STM32_SRC_PLL1_Q (STM32_SRC_PLL1_P + 1)
Dstm32u5_clock.h30 #define STM32_SRC_PLL1_P (STM32_SRC_PCLK3 + 1) macro
31 #define STM32_SRC_PLL1_Q (STM32_SRC_PLL1_P + 1)
Dstm32h5_clock.h29 #define STM32_SRC_PLL1_P (STM32_SRC_PCLK3 + 1) macro
30 #define STM32_SRC_PLL1_Q (STM32_SRC_PLL1_P + 1)
/Zephyr-latest/drivers/clock_control/
Dclock_stm32_ll_wba.c56 ((src_clk == STM32_SRC_PLL1_P) && IS_ENABLED(STM32_PLL_P_ENABLED)) || in enabled_clock()
226 case STM32_SRC_PLL1_P: in stm32_clock_control_get_subsys_rate()
Dclock_stm32_ll_h5.c132 ((src_clk == STM32_SRC_PLL1_P) && IS_ENABLED(STM32_PLL_P_ENABLED)) || in enabled_clock()
282 case STM32_SRC_PLL1_P: in stm32_clock_control_get_subsys_rate()
Dclock_stm32_ll_u5.c138 ((src_clk == STM32_SRC_PLL1_P) && IS_ENABLED(STM32_PLL_P_ENABLED)) || in enabled_clock()
297 case STM32_SRC_PLL1_P: in stm32_clock_control_get_subsys_rate()
Dclock_stm32_ll_h7.c369 ((src_clk == STM32_SRC_PLL1_P) && IS_ENABLED(STM32_PLL_P_ENABLED)) ||
554 case STM32_SRC_PLL1_P: