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Searched full:otghs_sel (Results 1 – 3 of 3) sorted by relevance

/Zephyr-latest/dts/bindings/phy/
Dst,stm32u5-otghs-phy.yaml24 <&rcc STM32_SRC_HSE OTGHS_SEL(0)>;
28 <&rcc (STM32_SRC_HSE | STM32_CLOCK_DIV(2)) OTGHS_SEL(2)>;
32 <&rcc STM32_SRC_PLL1_P OTGHS_SEL(1)>;
36 <&rcc (STM32_SRC_PLL1_P | STM32_CLOCK_DIV(2)) OTGHS_SEL(3)>;
/Zephyr-latest/dts/arm/st/u5/
Dstm32u595.dtsi120 <&rcc STM32_SRC_HSE OTGHS_SEL(0)>;
/Zephyr-latest/include/zephyr/dt-bindings/clock/
Dstm32u5_clock.h125 #define OTGHS_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 30, CCIPR2_REG) macro