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/Zephyr-latest/kernel/
DKconfig.mem_domain20 This hidden option is selected by the target architecture if
21 architecture-specific data is needed on a per memory domain basis.
22 If so, the architecture defines a 'struct arch_mem_domain' which is
23 embedded within every struct k_mem_domain. The architecture
33 This hidden option is selected by the target architecture if
36 into the architecture layer.
38 If enabled, the architecture layer must implement the following
60 This hidden option is selected by the target architecture if
61 the architecture supports isolating thread stacks for threads
DKconfig.smp20 for an SMP-aware scheduler, or if the architecture does not
22 architecture provides both, _arch_switch incurs more somewhat
38 (architecture/SoC/board/application) to boot secondary CPUs at
52 True if the architecture supports a call to arch_sched_broadcast_ipi()
91 application behavior. If the architecture also supports directing
/Zephyr-latest/arch/
DKconfig1 # General architecture configuration options
16 # Architecture symbols
29 ARC architecture
42 ARM architecture
60 ARM64 (AArch64) architecture
67 MIPS architecture
80 SPARC architecture
104 x86 architecture
113 Nios II Gen 2 architecture
131 RISCV architecture
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/Zephyr-latest/scripts/tests/twister/
Dtest_quarantine.py23 ['dummy architecture', 'another architecture'],
31 ['dummy architecture', 'another architecture'],
39 ['all', 'another architecture'],
221 'scenario, platform, architecture, simulation, expected_idx',
234 architecture, argument
265 architecture=architecture,
272 architecture=architecture,
/Zephyr-latest/arch/arm/core/cortex_a_r/
DKconfig153 From https://developer.arm.com/products/architecture/cpu-architecture/r-profile:
154 The Armv7-R architecture implements a traditional Arm architecture with
155 multiple modes and supports a Protected Memory System Architecture
175 From https://developer.arm.com/products/architecture/cpu-architecture/r-profile:
176 The Armv8-R architecture targets at the Real-time profile. It introduces
178 Protected Memory System Architecture (PMSA) based on a Memory Protection
/Zephyr-latest/doc/services/dsp/
Dindex.rst10 The DSP API provides an architecture agnostic way for signal processing.
11 Currently, the API will work on any architecture but will likely not be
15 Architecture Status
44 Optimizing for your architecture
47 If your architecture is showing as ``Unoptimized``, it's possible to add a new
53 linked in at :file:`subsys/dsp/CMakeLists.txt`. To add architecture-specific attributes,
/Zephyr-latest/include/zephyr/arch/arm/
Dstructs.h12 /* Per CPU architecture specifics */
19 /* Default definitions when no architecture specific definitions exist. */
21 /* Per CPU architecture specifics (empty) */
/Zephyr-latest/doc/hardware/porting/
Darch.rst3 Architecture Porting Guide
6 An architecture port is needed to enable Zephyr to run on an :abbr:`ISA
7 (instruction set architecture)` or an :abbr:`ABI (Application Binary
20 An architecture port can be divided in several parts; most are required and
23 * **The early boot sequence**: each architecture has different steps it must
26 * **Interrupt and exception handling**: each architecture handles asynchronous
33 and architecture-dependent, and thread abortion possibly as well (required).
36 controller are tied to the architecture (some required, some optional).
39 architecture-specific implementation for performance reasons (required).
44 * **Fault management**: for implementing architecture-specific debug help and
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/Zephyr-latest/samples/net/dsa/
DREADME.rst2 :name: DSA (Distributed Switch Architecture)
5 Test and debug Distributed Switch Architecture
10 Example on testing/debugging Distributed Switch Architecture
/Zephyr-latest/samples/arch/
Dindex.rst2 :name: Architecture-dependent Samples
5 Samples that demonstrate some architecture-specific features.
/Zephyr-latest/arch/posix/core/
Dposix_core_nsi.c10 * This posix architecture "bottom" will be used when building with the native simulator.
18 * Initialize the posix architecture
27 * Clear the state of the POSIX architecture
/Zephyr-latest/kernel/include/
Dkernel_arch_interface.h9 * @brief Internal kernel APIs implemented at the architecture layer.
11 * Not all architecture-specific defines are here, APIs that are used
30 * @defgroup arch-timing Architecture timing APIs
35 * Architecture-specific implementation of busy-waiting
45 * @defgroup arch-threads Architecture thread APIs
88 * by the architecture. It is the same data structure stored in the
123 * architecture code to assume that it has any particular value at any
185 * @note For ARM architecture, disabling floating point preservation may only
199 * This API depends on each architecture implementation. If the architecture
206 * @param options architecture dependent options
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/Zephyr-latest/boards/native/doc/
Darch_soc.rst3 The POSIX architecture
14 The native simulator in combination with the POSIX architecture and the inf_clock SOC layer,
15 provide the foundation, architecture and SOC layers for a set of virtual test
22 Zephyr application, eliminating the need for architecture-specific
27 The POSIX architecture is not related and should not be confused with the
61 The POSIX architecture is known to **not** work on macOS due to
97 `Rationale for this port`_ and :ref:`Architecture<posix_arch_architecture>`
177 Currently, these are the most significant features which are not supported in this architecture:
188 :ref:`the architecture section's architecture layer paragraph <posix_arch_design_archl>`
240 This native port compiles your code directly for the host architecture
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Dbsim_boards_design.rst17 This page covers the design, architecture and rationale, of the
21 These boards use the `native simulator`_ and the :ref:`POSIX architecture<Posix arch>` to build
73 With the POSIX architecture we provided an overall
113 The :ref:`native_sim <native_sim>` board shares the :ref:`POSIX architecture<Posix arch>`,
154 The basic architecture layering of these boards is as follows:
157 - The architecture, SOC and board components of Zephyr are replaced with
159 - The architecture (arch) is the Zephyr :ref:`POSIX architecture<Posix arch>`
163 - The POSIX architecture provides an adaptation from the Zephyr arch API
166 See :ref:`POSIX arch architecture<posix_arch_architecture>`
191 Overall architecture in a Zephyr application in an embedded target vs a bsim
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/Zephyr-latest/doc/services/pm/
Doverview.rst5 are designed to be architecture and SOC independent. This enables power
9 The architecture and SOC independence is achieved by separating the core PM
/Zephyr-latest/subsys/testsuite/arch/unit_testing/
DKconfig11 The unit_testing architecture identifies itself as X86 for basic
21 The unit testing architecture is expected to always have access to a
/Zephyr-latest/arch/arm64/core/
DKconfig207 From https://developer.arm.com/products/architecture/cpu-architecture/a-profile:
208 The Armv8-A architecture introduces the ability to use 64-bit and
214 compatibility with the Armv7-A architecture and enhances that profile
233 From https://developer.arm.com/products/architecture/cpu-architecture/r-profile:
234 The Armv8-R architecture targets at the Real-time profile. It introduces
236 Protected Memory System Architecture (PMSA) based on a Memory Protection
Dcoredump.c10 /* Identify the version of this block (in case of architecture changes).
11 * To be interpreted by the target architecture specific block parser.
15 /* Structure to store the architecture registers passed arch_coredump_info_dump
55 /* Target architecture information header */ in arch_coredump_info_dump()
/Zephyr-latest/dts/bindings/
Dbinding-types.txt20 arc ARC architecture
21 arm ARM architecture
44 dsa DSA (Distributed Switch Architecture)
97 ppc PPC architecture
106 riscv RISC-V architecture
/Zephyr-latest/include/zephyr/
Dfatal.h32 * Invokes architecture-specific code to power off or halt the system in
46 * unconditionally. Depending on architecture support, this may be
71 * @brief Called by architecture code upon a fatal error.
73 * This function dumps out architecture-agnostic information about the error
/Zephyr-latest/include/zephyr/arch/
Dstructs.h8 * The purpose of this file is to provide essential/minimal architecture-
36 /* Default definitions when no architecture specific definitions exist. */
38 /* Per CPU architecture specifics (empty) */
/Zephyr-latest/drivers/ethernet/
DKconfig.dsa1 # Distributed Switch Architecture [DSA] configuration options
13 bool "Distributed Switch Architecture support"
16 Enable Distributed Switch Architecture support. For now it
/Zephyr-latest/doc/kernel/services/other/
Dfloat.rst12 the Intel x86 architecture, the SPARC architecture and ARCv2 SoCs
14 are architecture specific.
59 floating point registers. Depending upon the underlying CPU architecture,
75 ARM Cortex-M architecture (with the Floating Point Extension)
82 On the ARM Cortex-M architecture with the Floating Point Extension, the kernel
118 architecture, minimizing interrupt latency, when the floating
136 ARM64 architecture
145 On the ARM64 (Aarch64) architecture the kernel treats each thread as a FPU
162 ARCv2 architecture
165 On the ARCv2 architecture, the kernel treats each thread as a non-user
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/Zephyr-latest/doc/services/llext/
Dindex.rst24 The LLEXT subsystem requires architecture-specific support. It is currently
26 Harvard architecture cores that separate code and data paths and have no
/Zephyr-latest/arch/arm64/
DKconfig1 # ARM64 architecture configuration options
28 When this option is selected, the architecture interrupt control

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